A Circuit Simulation Method Based on Incremental Compilation

Abstract

A circuit simulation method based on incremental compilation, comprising the following steps: 1) analyzing simulation tasks and performing group precompilation, and putting the precompiled simulation tasks into a process pool; 2) starting each process pool in a distributed manner 3) for each simulation process, find the compilation information table corresponding to the group according to the group number; 4) analyze the netlist file and perform incremental compilation according to the compilation information table; 5) analyze according to the compilation information table Simulation option and perform incremental compilation; 6) add group number to each remaining task in the group to form a simulation process, collect all simulation processes and put them into the process pool, return to execute step 2) until the simulation task ends. The circuit simulation method based on incremental compilation of the present invention considers the correlation of data between different simulation tasks, uses the incremental compilation mechanism to share compiled data, thereby saving compilation time, reducing the peak value of memory during compilation, and effectively improving the overall simulation efficiency.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a method for distributed simulation of integrated circuits using incremental compilation. Background technique [0002] The general workflow of the traditional analog integrated circuit simulator is: 1. Read the circuit netlist for lexical analysis (Parsing); 2. Calculate parameters, establish circuit topology, and topology reduction (Elaboration); 3. Divide the circuit ( Partition); 4. Establish matrix, solve equation (Solving); 5. Output. Processes 1, 2, and 3 are relatively independent from 4 and 5. 1, 2, and 3 can be regarded as compilation or interpretation, and 4 and 5 can be regarded as running. For large-scale circuits, although the running part occupies the bulk of the simulation time, the absolute time and memory peak occupied by the compilation are considerable: tens of hours and hundreds of GB, respectively. For smaller circuits, the run time is ge...

AI Technical Summary

Problems solved by technology

[0004] Traditional emulators make compiling and running an uninterruptible serial pipeline, that is, a simulation task is a process from compiling to running, and there is no communication between different tasks, so compiling and sharing cannot be achieved

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