Transmitter with low-speed SerDes interface, receiver and circuit design method thereof

Abstract

The invention provides a transmitter with a low-speed SerDes interface, a receiver with a low-speed SerDes interface and a circuit design method of the transmitter and the receiver. The transmitter comprises a SerDes analog circuit and a SerDes digital circuit, and the SerDes digital circuit comprises a four-frequency division module which is used for performing four-frequency division on a SerDes parallel data transmission clock tx_clk_20t generated by the SerDes analog circuit to generate a parallel data transmission clock pma_tx_clk of a controller and inputting the parallel data transmission clock pma_tx_clk to a protocol controller; an asynchronous FIFO module which is used for carrying out cross-asynchronous reading on the data from the protocol controller; a tx_data_repeat_gen module which is used for repeatedly sending each bit in the data rd_data_40 with the bit width of 40 bits read by the asynchronous FIFO module for one time, so as to obtain data tx_data_80 with the bit width of 80 bits; a bit width conversion module which is used for carrying out bit width conversion from 80_bit to 20_bit on the data tx_data_80 output by the tx_data_repeat_gen module; a SerDes analog circuit which is used for carrying out parallel-serial conversion processing on the data output by the bit width conversion module and sending out the data through a high-speed differential serial channel line TX_P / TX_N of the SerDes analog circuit, and generating a SerDes parallel data sending clock tx_clk_20t.

Description

technical field [0001] The invention relates to the technical field of SerDes, in particular to a transmitter with a low-speed SerDes interface, a receiver and a circuit design method thereof. Background technique [0002] With the continuous development of science and technology, in the field of electronic communication, the technology of transmitting data is constantly improving, and the transmission rate is also constantly accelerating. SerDes (Serializer / Deserializer, Serializer / Deserializer) technology is a major invention in the field of high-speed serial data transmission. The origin of the name SerDes is a combination of the words Serlializer and Deserializer. SerDes is a typical digital-analog hybrid system. At present, SerDes mainly adopts a self-synchronization method, that is, the data transmitted by the interface contains clock information, which is completed by the Clock Data Recovery (CDR) circuit at the receiving end (Rx). The clock extraction and data re-s...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problems of high cost and high risk of adapting new technology in re-researching and developing 1.0625Gbps SerDes interface IP under the existing manufacturing process, or transplanting the old 1.0625Gbps SerDes interface IP to the new manufacturing process, the present invention Provide a transmitter with low-speed SerDes interface, receiver and circuit design method thereof

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