Transmitter with low-speed SerDes interface, receiver and circuit design method thereof

A transmitter and receiver technology, applied in the field of SerDes, can solve problems such as high cost and high risk of adapting new technologies, and achieve the effects of ensuring integrity, reducing design risk and cost, and ensuring no error codes

Active Publication Date: 2021-10-29
PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Aiming at the problems of high cost and high risk of adapting new technology in re-researching and developing 1.0625Gbps SerDes interface IP under the existing manufacturing process, or transplanting the old 1.0625Gbps SerDes interface IP to the new manufacturing process, the present invention Provide a transmitter with low-speed SerDes interface, receiver and circuit design method thereof

Method used

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  • Transmitter with low-speed SerDes interface, receiver and circuit design method thereof
  • Transmitter with low-speed SerDes interface, receiver and circuit design method thereof
  • Transmitter with low-speed SerDes interface, receiver and circuit design method thereof

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Effect test

Embodiment 1

[0043] The basic structure of the existing SerDes transmitter circuit is as follows: figure 1 As shown, the SerDes analog part circuit generates the SerDes parallel data transmission clock tx_clk_20t according to the rate configuration. The clock frequency is the rate / parallel data bit width, and the SerDes parallel data bit width is 20 bits. Therefore, when the rate configuration is 8.5G, tx_clk_20t = 425Mhz (8.5 G / 20bit); when the rate configuration is 4.25G, tx_clk_20t = 212.5Mhz (4.25G / 20bit); when the rate configuration is 2.125G, tx_clk_20t = 106.25Mhz (2.125G / 20bit). Since the FC controller transmits data with a parallel bit width of 40 bits, the SerDes digital part first divides tx_clk_20t by two to generate the controller’s parallel data transmission clock pma_tx_clk (53.125Mhz) and inputs it to the FC controller for 40-bit parallel data transmission, and then the FC The data sent by the controller is read across asynchronously through the asynchronous FIFO, and then ...

Embodiment 2

[0046] The basic structure of the existing SerDes receiver circuit is as follows: image 3 As shown, the SerDes analog part circuit generates the SerDes parallel data receiving clock rx_clk_20t according to the rate configuration. The clock frequency is rate / parallel data bit width, and the SerDes parallel data bit width is 20 bits. Therefore, when the rate configuration is 8.5G, rx_clk_20t = 425Mhz (8.5 G / 20bit); when the rate configuration is 4.25G, rx_clk_20t = 212.5Mhz (4.25G / 20bit); when the rate configuration is 2.125G, rx_clk_20t = 106.25Mhz (2.125G / 20bit). The SerDes analog circuit first converts the high-speed differential serial data received from RX_P / RX_N into 20-bit parallel data rx_data_20, and at the same time generates a 20t SerDes parallel data receiving clock rx_clk_20t. Since the FC controller receives data parallel bit width is 40 bits, the SerDes digital First, rx_clk_20t is divided by two to generate the parallel data receiving clock rx_par_clk (53.125Mhz...

Embodiment 3

[0049] Based on the same design principle as Embodiment 1, this embodiment of the present invention also provides a transmitter with a 1.25Gbps low-speed SerDes interface. The difference from Embodiment 1 is that this embodiment of the present invention is based on the existing 2.5Gbps SerDes transmitter circuit For the design, the rate of the SerDes analog circuit is configured to be 2.5Gbps, and the protocol controller is adjusted to be an SRIO controller. The other contents are the same as those in Embodiment 1, and will not be repeated here.

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Abstract

The invention provides a transmitter with a low-speed SerDes interface, a receiver with a low-speed SerDes interface and a circuit design method of the transmitter and the receiver. The transmitter comprises a SerDes analog circuit and a SerDes digital circuit, and the SerDes digital circuit comprises a four-frequency division module which is used for performing four-frequency division on a SerDes parallel data transmission clock tx_clk_20t generated by the SerDes analog circuit to generate a parallel data transmission clock pma_tx_clk of a controller and inputting the parallel data transmission clock pma_tx_clk to a protocol controller; an asynchronous FIFO module which is used for carrying out cross-asynchronous reading on the data from the protocol controller; a tx_data_repeat_gen module which is used for repeatedly sending each bit in the data rd_data_40 with the bit width of 40 bits read by the asynchronous FIFO module for one time, so as to obtain data tx_data_80 with the bit width of 80 bits; a bit width conversion module which is used for carrying out bit width conversion from 80_bit to 20_bit on the data tx_data_80 output by the tx_data_repeat_gen module; a SerDes analog circuit which is used for carrying out parallel-serial conversion processing on the data output by the bit width conversion module and sending out the data through a high-speed differential serial channel line TX_P / TX_N of the SerDes analog circuit, and generating a SerDes parallel data sending clock tx_clk_20t.

Description

technical field [0001] The invention relates to the technical field of SerDes, in particular to a transmitter with a low-speed SerDes interface, a receiver and a circuit design method thereof. Background technique [0002] With the continuous development of science and technology, in the field of electronic communication, the technology of transmitting data is constantly improving, and the transmission rate is also constantly accelerating. SerDes (Serializer / Deserializer, Serializer / Deserializer) technology is a major invention in the field of high-speed serial data transmission. The origin of the name SerDes is a combination of the words Serlializer and Deserializer. SerDes is a typical digital-analog hybrid system. At present, SerDes mainly adopts a self-synchronization method, that is, the data transmitted by the interface contains clock information, which is completed by the Clock Data Recovery (CDR) circuit at the receiving end (Rx). The clock extraction and data re-s...

Claims

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Application Information

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IPC IPC(8): H04B1/04H04B1/16H04L29/06
CPCH04B1/04H04B1/16H04L69/18
Inventor 张传波吕平刘勤让虎艳宾李沛杰张丽沈剑良张帆张文建丁瑞浩
Owner PLA STRATEGIC SUPPORT FORCE INFORMATION ENG UNIV PLA SSF IEU
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