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Semiconductor packaging test system and method

A technology for packaging testing and testing systems, applied in semiconductor/solid-state device testing/measurement, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as poor impedance change welding, easy deformation of pins, and difficult alignment, etc., to achieve Electronic archiving is convenient and simplifies the effect of testing equipment

Pending Publication Date: 2021-11-12
东莞先导先进科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] Many semiconductor packages need to be tested by simulating their applicable environment. However, it is difficult to simulate the performance test of semi-finished products in the field of infrared detectors. The existing technology only relies on appearance defects to judge whether it is good or bad.
This is difficult to accurately observe hidden defects caused by unstable manufacturing processes, such as microcracks, electrostatic breakdown, impedance changes caused by foreign objects, micro-breaks, short circuits, and poor welding.
Since most factories generally adopt automation to put into production, the production process is likely to cause poor batch quality in the next process
And the test parameters cannot be saved and traced, and the quality product test information cannot be effectively and quickly traced and located
At the same time, in the field of DIP package testing, the pins are easy to deform and difficult to align, and it is more difficult to align single-sided and double-row pins, and the testing process is easy to cause deformation of the pins

Method used

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  • Semiconductor packaging test system and method
  • Semiconductor packaging test system and method
  • Semiconductor packaging test system and method

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Embodiment Construction

[0076] In order to facilitate the understanding of the present invention, the present invention will be described more fully and in detail below in conjunction with the accompanying drawings and preferred embodiments, but the protection scope of the present invention is not limited to the following specific embodiments.

[0077] Unless otherwise defined, all professional terms used hereinafter have the same meaning as commonly understood by those skilled in the art. The terminology used herein is only for the purpose of describing specific embodiments, and is not intended to limit the protection scope of the present invention.

[0078] Unless otherwise specified, various elements and devices used in the present invention can be purchased from the market or prepared by existing methods.

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Abstract

The invention discloses a semiconductor packaging test system and method. The test system comprises a constant current circuit for providing a constant current for a semiconductor packaging pin, a sampling circuit used for measuring the voltage-to-ground value of each pin of the semiconductor package, an amplifying circuit used for amplifying the voltage-to-ground signal of each pin of the semiconductor package, an A / D conversion circuit which is connected with the output end of the amplifying circuit and converts an analog signal into a digital signal, and a control unit used for judging whether the quality of the semiconductor package is qualified or not according to the received digital signal of the A / D conversion circuit. According to the invention, a set of complete semiconductor packaging test path including fixing, measuring, displaying and alarming is developed, the test is simple and convenient, the problem that a semiconductor packaging use environment is difficult to simulate is solved, and the problem that test alignment is difficult is solved too. The test method is accurate in measurement and simplified in matching, has a wide engineering practical value, and is particularly suitable for testing infrared detector type chips.

Description

technical field [0001] The present invention relates to the field of semiconductor packaging performance parameter testing, and more specifically, to a semiconductor packaging testing system and method. Background technique [0002] In the semiconductor COB (Cip on Board) packaging field, the gold wire and the wafer Wire Bond process are used to connect with the external circuit. [0003] Many semiconductor packages need to be tested by simulating their applicable environment. However, it is difficult to simulate the performance test of semi-finished products in the field of infrared detectors. The existing technology only relies on appearance defects to judge whether it is good or bad. This is difficult to accurately observe hidden defects caused by unstable manufacturing processes, such as microcracks, electrostatic breakdown, impedance changes caused by foreign objects, micro-breaks, short circuits, and poor welding. Since most factories generally adopt automation to put...

Claims

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Application Information

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IPC IPC(8): H01L21/66H01L21/687
CPCH01L22/14H01L22/20H01L21/6875
Inventor 刘志双曾广锋高涛陈玉成
Owner 东莞先导先进科技有限公司