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System-level testing device for high-speed serial differential bus of SOC ship

A test device, high-speed serial technology, applied in faulty hardware testing methods, error detection/correction, detection of faulty computer hardware, etc. The effect of high efficiency and reduced requirements

Pending Publication Date: 2021-11-16
北京炬力北方微电子股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] With the popularization of high-speed serial differential buses such as HDMI, LVDS, USB, Ethernet, MIPI, and PCIE, SOC chips in the field of consumer electronics gradually integrate these high-speed serial buses to improve integration and reduce costs. The mass production test brings challenges! Various high-speed serial differential signal tests of current consumer SOC chips need to be completed by dedicated radio frequency integrated circuit automatic test equipment (Automatic Test Equipment, ATE), which makes the test cost high and development difficult, which is very unsuitable for consumer SOC. Low cost and rapid development pursued by mass production testing of chips

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  • System-level testing device for high-speed serial differential bus of SOC ship
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  • System-level testing device for high-speed serial differential bus of SOC ship

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Embodiment Construction

[0062] Referring to the drawings, wherein like reference numerals represent like components, the principles of the present invention are exemplified when implemented in a suitable computing environment. The following description is based on illustrated specific embodiments of the invention, which should not be construed as limiting other specific embodiments of the invention not described in detail herein.

[0063] refer to figure 1 , the system-level test device 100 of the SOC chip high-speed serial differential bus of an embodiment of the present invention can realize the system-level test to the SOC chip, and the system-level test device 100 includes a backplane bus, a first board 11 and a second Board 12.

[0064] The first plate card 11 comprises a main control communication module 13, a DUT control test module 14 and at least one functional test module group, wherein each functional test module group includes an HDMI TX functional test module 15, an HDMI RX functional t...

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Abstract

The embodiment of the invention discloses a system-level testing device for a high-speed serial differential bus of an SOC chip. The system-level testing device comprises a backboard bus, a first board card and a second board card; the first board card comprises a main control communication module, a DUT control test module and at least one function test module group, and each function test module group comprises an HDMI TX function test module, an HDMI RX function test module, an LVDS TX function test module, a USB function test module and a network port function test module; and the second board card comprises at least one SOC chip socket, each SOC chip socket is used for loading a tested SOC chip, and the HDMITX function test module, the HDMI RX function test module, the LVDS TX function test module, the USB function test module and the network port function test module are respectively used for performing communication function test on corresponding ports of the tested SOC chips. By means of the mode, the requirement for ATE can be lowered in the high-speed signal test, and the test cost is lowered.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to a system-level testing device for a SOC chip high-speed serial differential bus. Background technique [0002] With the popularization of high-speed serial differential buses such as HDMI, LVDS, USB, Ethernet, MIPI, and PCIE, SOC chips in the field of consumer electronics gradually integrate these high-speed serial buses to improve integration and reduce costs. The mass production test of the posed a challenge! Various high-speed serial differential signal tests of current consumer SOC chips need to be completed by dedicated radio frequency integrated circuit automatic test equipment (Automatic Test Equipment, ATE), which makes the test cost high and development difficult, which is very unsuitable for consumer SOC. The low cost and rapid development pursued by mass production testing of chips. Contents of the invention [0003] The embodiment of the present invention pro...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/22G06F11/263
CPCG06F11/221G06F11/2273G06F11/263Y02D10/00
Inventor 袁科学
Owner 北京炬力北方微电子股份有限公司