Multi-strategy optimization-based multi-layer overall wiring method for super-large-scale integrated circuit

A large-scale integrated circuit and overall wiring technology, applied in design optimization/simulation, CAD circuit design, calculation model, etc., can solve the problems of harsh wiring technology precision, shorten the overall wiring bus length, respond flexibly, and avoid the search process redundant effect

Active Publication Date: 2021-11-16
FUZHOU UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, VLSI's requirements for its design process are gradually increasing, and the precision of wiring technology is also more demanding.

Method used

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  • Multi-strategy optimization-based multi-layer overall wiring method for super-large-scale integrated circuit
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  • Multi-strategy optimization-based multi-layer overall wiring method for super-large-scale integrated circuit

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Embodiment Construction

[0051] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0052] It should be pointed out that the following detailed descriptions are all exemplary, and are intended to provide further explanation to the application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0053] It should be noted that the terminology used here is only for describing specific implementations, and is not intended to limit the exemplary implementations according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should also be understood that when the terms "comprises" and / or "comprises" are used in this specification, they indicate There are features, steps, operations, means...

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Abstract

The invention relates to a multi-strategy optimization-based multi-layer overall wiring method for a super-large-scale integrated circuit. The method comprises the following steps: S1, in a pre-connection wiring stage, properly adjusting and reducing channel capacity by adopting a dynamic adjustment strategy of virtual capacity; S2, finding a most crowded wiring area in a wiring recombination stage under global consideration, carrying out adaptive expansion on the most crowded wiring area by adopting an adaptive expansion strategy of a wiring sub-area, and correspondingly adjusting an expansion range and an expansion speed according to different congestion degrees after wiring; S3, dynamically adjusting the channel virtual capacity by adopting a dynamic adjustment strategy of the virtual capacity during wiring, mutually supplementing the channel capacities in different channel directions, and timely supplementing the remaining wiring channels with smaller channel capacities; and S4, adopting a heuristic search strategy based on the A* algorithm to carry out heuristic search and wiring through the A * algorithm. According to the invention, the utilization rate of wiring capacity can be improved, and the wiring efficiency of the wiring device and the global search pressure are balanced.

Description

technical field [0001] The invention relates to the technical field of computer-aided design of integrated circuits, in particular to a multi-layer overall wiring method for ultra-large-scale integrated circuits based on multi-strategy optimization. Background technique [0002] Chip design is one of the world's most subtle and grand projects, integrating tens of billions of "switches" that allow or block current flow into a chip the size of a fingernail. From the micron level to the nano level, it is the engineering extreme that human beings are constantly climbing. In chip design, VLSI is the key to the design process, and it can be used to manufacture electronic devices with small size, light weight, low power consumption but rich functions and high reliability. At the beginning, the integration level of chip circuits was not high, and developers could rely on hand-drawn circuits, but now chips containing hundreds of millions or even tens of billions of transistors, if t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3947G06F30/398G06F30/27G06N20/00G06F115/06
CPCG06F30/3947G06F30/398G06F30/27G06N20/00G06F2115/06
Inventor 刘耿耿裴镇宇郭文忠郑筱媛陈国龙
Owner FUZHOU UNIV
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