Embedded word line structure preparation method

A buried word line and trench technology, used in semiconductor/solid-state device manufacturing, static memory, instruments, etc., can solve the problem of uneven etching of semiconductor substrates, difficult to control the etching environment, and easy access to the bottom of the first trench. Problems with tips or glitches

Pending Publication Date: 2021-11-19
CHANGXIN MEMORY TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, during the etching of the semiconductor substrate, due to the difficulty in controlling the etching environment inside the first trench, the etching of the semiconductor substrate at different positions is not uniform, and the bottom of the first trench formed by etching is uneven. Groove bottoms are prone to spikes or burrs

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  • Embedded word line structure preparation method
  • Embedded word line structure preparation method
  • Embedded word line structure preparation method

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Embodiment Construction

[0045] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the associated drawings. A preferred embodiment of the invention is shown in the drawings. However, the present invention can be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0047] Such a...

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Abstract

The invention relates to an embedded word line structure and a preparation method thereof, and the preparation method comprises the steps: forming a first groove in a semiconductor substrate, and enabling the bottom of the first groove to be provided with a tip; carrying out epitaxial growth in the first groove, and reducing the depth of the tip of the bottom of the first groove; and forming a gate dielectric layer on the inner wall of the first groove and filling a gate conductive layer in the first groove to form an embedded word line structure. According to the preparation method, the tip depth of the first groove is reduced through the epitaxial growth process, so that the tip discharge phenomenon is weakened, and the device performance is improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for preparing a buried word line structure. Background technique [0002] In the semiconductor process, the conventional procedure for forming a buried word line structure is: etching the semiconductor substrate to open a first trench on the semiconductor substrate, and filling the first trench with a word line structure to form a buried word line structure. type word line structure. However, during the etching of the semiconductor substrate, since the etching environment inside the first trench is difficult to control, the etching of the semiconductor substrate at different positions is not uniform, and the bottom of the first trench formed by etching is uneven. The bottom of the groove is prone to points or burrs. For a semiconductor device, a tip appears at the bottom of the word line, and a tip discharge is likely to occur and damage the semiconductor device. Conten...

Claims

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Application Information

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IPC IPC(8): H01L21/8242H01L27/108
CPCH10B12/30H10B12/488G11C5/063H01L29/4236H01L29/66621H01L29/42376H01L21/76232H01L29/401H01L29/42364
Inventor 陆勇沈宏坤
Owner CHANGXIN MEMORY TECH INC
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