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Semiconductor device

A semiconductor and active area technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., and can solve problems such as inability to meet requirements

Pending Publication Date: 2021-11-30
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While the existing structure used for the tap unit was suitable for its intended purpose, it did not meet all requirements

Method used

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  • Semiconductor device
  • Semiconductor device
  • Semiconductor device

Examples

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Embodiment Construction

[0061] The above detailed description can be accompanied by accompanying drawings to facilitate understanding of aspects of the present invention. It is worth noting that various structures are used for illustration purposes only and are not drawn to scale, as is the norm in the industry. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of illustration.

[0062] Different embodiments or examples provided in the following content can implement different structures of the embodiments of the present invention. The examples of specific components and arrangements are used to simplify the disclosure and not to limit the invention. For example, the statement that the first component is formed on the second component includes that the two are in direct contact, or there are other additional components interposed between the two instead of direct contact. In addition, various examples of the present invention may repeatedly use ...

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PUM

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Abstract

A semiconductor device includes an active region including a channel region and a source / drain region adjacent to the channel region, a vertical stack of a plurality of channel features, a gate structure, a bottom dielectric structure, a source / drain structure, and a germanium layer. A vertical stack of a plurality of channel features is on the channel region. A gate structure is located around and over the vertical stack of channel features. The bottom dielectric structure is on the source / drain region. The source / drain structure is on the bottom dielectric structure. The germanium layer is located between the bottom dielectric structure and the source / drain region.

Description

technical field [0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to a method of forming a semiconductor oxide structure under a source / drain structure to obtain a pseudo-silicon-on-insulator structure. Background technique [0002] The semiconductor integrated circuit industry has experienced exponential growth. Technological advances in integrated circuit materials and design have resulted in each generation of integrated circuits having smaller and more complex circuits than the previous generation. In the evolution of integrated circuits, functional density (eg, the number of interconnect devices per unit chip area) generally increases as geometric dimensions (eg, the smallest component or circuit that can be produced by the fabrication process employed) shrink. Downsizing is often beneficial in increasing capacity and reducing associated costs. Shrinking dimensions also increase the complexity of handling and manufactur...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78H01L27/088
CPCH01L29/7831H01L29/785H01L27/088H01L27/0886H01L29/0649H01L29/0653B82Y10/00H01L29/0673H01L29/0847H01L29/1083H01L29/42392H01L29/66439H01L29/775H01L29/78696H01L21/02236H01L21/02532H01L21/02603H01L21/823807H01L21/823814H01L21/823864H01L27/0921H01L29/66545H01L29/66553H01L29/66742H01L29/78612H01L29/78618
Inventor 陈仕承江国诚林志昌
Owner TAIWAN SEMICON MFG CO LTD