Data reading method and device in host performance acceleration mode

Abstract

The invention relates to a data reading method and device in a host performance acceleration mode. The method is executed by a host end, and comprises the steps: obtaining a value of a dedicated data register of an expansion device in a flash memory controller from the flash memory controller; and when the value of the expansion device dedicated data register contains the information supporting the host performance acceleration function, configuring a space in the system memory as a host performance acceleration buffer, and storing a plurality of logical and physical contrast records acquired from the flash memory controller in the host performance acceleration buffer. The host end and the flash memory controller communicate with each other by using an embedded multimedia card communication protocol, and each logic physical contrast records information of data of a storage logic address actually stored in a physical address. According to the invention, the host end can send the read command with the logic and physical comparison record to the flash memory controller through the arrangement of the host efficiency acceleration buffer area, so that the time and operation resources spent by the flash memory controller are reduced to carry out logic and physical comparison conversion.

Description

technical field [0001] The invention relates to a storage device, in particular to a method and device for reading data in a host performance acceleration mode. Background technique [0002] Flash memory is usually divided into NOR flash memory and NAND flash memory. The NOR flash memory is a random access device. The central processing unit (Host) can provide any address for accessing the NOR flash memory on the address pin, and obtain the data stored at the address from the data pin of the NOR flash memory in time. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory cannot access any random address like NOR flash memory. Instead, the central processor needs to write the value of serial bytes (Bytes) into NAND flash memory to define the type of request command (Command) (such as, read, write, erase, etc.), and the address used on this command. The address can point to a page (the smallest data block for write operations in flash memo...

AI Technical Summary

Problems solved by technology

However, in an embedded Multi-Media Card (embedded Multi-Media Controller, e.MMC) storage device, with the rapid increase in device capacity, the length of the logical-physical comparison table is also multiplied, resulting in the traditional management method executed on the device side. unaffordable

Even if using hierarchical sub-areas to manage the logical-physical comparison table can improve the performance of logical-physical conversion, the time spent on logical-physical conversion is still significantly higher than that of transferring data from the flash memory array of the flash memory module to the data register of the flash memory controller. time (tR)

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