Semiconductor package including interposer

Abstract

A semiconductor package includes a processor; a bottom memory containing a plurality of bottom memory chips stacked vertically; an interposer mounted on the processor and a lower memory; and an upper memory mounted on the interposer, the upper memory comprising a plurality of upper memory chips that are stacked vertically. The interposer includes a first physical layer (PHY) that sends and receives a signal between the processor and the lower memory and sends and receives a signal between the processor and the upper memory. The processor includes a second PHY communicating with the first PHY and a first through silicon via (TSV) electrically connecting the first PHY to the second PHY.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2020-0093027 filed with the Korean Intellectual Property Office on July 27, 2020, the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including an interposer. Background technique [0004] As the electronics industry progresses, electronic devices are gradually miniaturized and adapted to perform multiple tasks, and thus, the speed and capacity of memories applied to electronic devices are increasing. [0005] System-in-Package (SiP) technology has been developed to increase performance and reduce cost of electronic devices. According to this technology, a semiconductor memory device is integrated into one package structure together with a processing unit, so one semiconductor package product ...

AI Technical Summary

Problems solved by technology

However, as the number of stacked semiconductor chips increases, a shift occurs due to a difference in physical distance between a memory chip disposed on the uppermost layer and a memory chip disposed on the lowermost layer ( s k ew ), resulting in a loss of electrical characteristics as the uppermost memory chip is farther away from the buffer chip than the lowermost memory chip

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