Vertical packaging structure with upper cup and lower cup

Abstract

The invention belongs to the field of semiconductor packaging, and discloses a vertical packaging structure with an upper cup and a lower cup; the structure comprises a circuit substrate, the circuit substrate is composed of a main substrate and two auxiliary substrates, the two auxiliary substrates are located on the left side and the right side of the main substrate respectively and spaced by a certain distance, and a functional chip is arranged on the top of the main substrate. The bottom of the main substrate is provided with an ASIC driving chip, the functional chip and the ASIC driving chip are respectively connected with two circuit connecting lines, the two circuit connecting lines on the functional chip are respectively connected with the two auxiliary substrates, and the two circuit connecting lines on the ASIC driving chip are respectively connected with the two auxiliary substrates. According to the scheme, a vertical integrated structure which is independently packaged or formed by double cups at a time is changed into a subtractive vertical packaging structure, so that the integration and miniaturization of a packaging device and the shortest electrical connection circuit are met, the process is mature and simple, and the yield can meet the requirement of large-scale mass production.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, more specifically, to a vertical packaging structure with upper and lower double cups. Background technique [0002] In recent years, related electronic terminal products tend to be miniaturized, portable and diversified in application space, especially the intelligence of various products and the development trend of the Internet of Everything, requiring many single-function components to be integrated or functional devices and control-driven modularity. Furthermore, a variety of interrelated components with different functions should be placed in a packaged device. For example, in optoelectronic semiconductors, light-emitting diodes (LEDs) and their control drivers (ASICs) are now two independent packaging devices. In the future packaging development, the integration of LEDs and ASICs is a trend. Similar is the integration of sensors with their ASICs and so on. [0003] Today's package...

AI Technical Summary

Problems solved by technology

The independent package is not conducive to the miniaturization of the product and the energy loss of the interconnection of components. The planar integrated package further integrates components of different functional types, and the size and electrical connection of the product are more optimized than the independent package. Because it is a planar The package size is the superposition of the size of multiple components, each component occupies a space independently, and the electrical connections are also connected one by one, and there are restrictions on the integrated size and electrical connection of components. , cannot further meet the needs of future products

[0004] Recently, different research institutions have developed additive vertical integrated packaging, which can greatly reduce the packaging space of components and shorten the electrical connection lines, but this packaging structure involves multi-layer circuits and insulating layers. Production, the vertical holes between the lines are connected to each other, the process is extremely complicated, so the yield rate has always been poor, and the cost remains high, making it difficult to achieve mass production

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