BGA entity packaging chip device and BGA entity packaging method

Abstract

The invention discloses a BGA entity packaging chip device and a BGA entity packaging method. The BGA entity packaging chip device comprises a chip and a radiator connected with the chip, pins of the chip comprise a power source backflow ground pin, a power source pin, a signal backflow ground pin and a signal pin, a part of the pins are arranged on one side of the chip, and the other part of the pins are arranged on the other surface of the chip. According to the invention, the size of the chip can be reduced by adjusting the position of the pins, so that the miniaturization design of an electronic product is facilitated.

Description

technical field [0001] The invention relates to the technical field of chip packaging, and more specifically, relates to a BGA entity packaging chip device. In addition, the present invention also relates to a BGA physical packaging method for manufacturing the above-mentioned BGA physical packaged chip device. Background technique [0002] With the rapid development of information technology in today's society, the design of electronic products is becoming more and more miniaturized and the functions are becoming more and more complex and powerful, which leads to the miniaturization of chip design and its selection in the circuit system, and with the The enhancement of chip functions and the increase in the number of chip pins usually also lead to an increase in power consumption of the chip, which leads to the need for efficient heat dissipation performance. Miniaturized chip package design and stable performance are the design difficulties in chip manufacturing at presen...

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Problems solved by technology

At the same time, the increase of chip functions also further leads to the increase of its power consumption, which in turn increases the power supply pins and power return ground pins in the chip package. Please refer to figure 1 , figure 1 It is the front view of the chip in the prior art. The pins 10 of the chip 1 include the power return pin 11, the power supply pin 14, the signal return pin 13 and the signal pin 12. The increase in the number of pins is not conducive to the board Wiring, which increases the difficulty of PCB layer and PCB design, increases the cost of PCB, and the increase of the power supply network in the chip has a great crosstalk effect on the surrounding signals, which poses a great risk to the signal transmission quality

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