Phase synchronization update without synchronization signal transmission

Abstract

The invention relates to phase synchronization updates without synchronization signal transmissions. Embodiments of the present disclosure provide systems and methods for implementing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute SYSREF signals over a high speed domain. In particular, the phase synchronization mechanism of the present invention is based on holding a first phase accumulator in the device clock domain and asynchronously transmitting a phase update to the final digital clock domain by using a second phase accumulator in the final digital clock domain. The arrival of a new SYSREF pulse may be detected based on a count value of the first phase accumulator, and the value is transmitted asynchronously and scaled to a downstream second phase delay adder. Thus, even if the SYSREF signal itself is not synchronously transmitted to the second phase delay adder, a phase update of the SYSREF signal can be transmitted downstream, so that a final phase can be deterministically generated.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of and priority to U.S. Patent Application No. 63 / 062,561, entitled "Phase Synchronous Updates Without Sync Signal Transmission," filed August 7, 2020, the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] The present disclosure relates generally to electronic devices, and more particularly to systems and methods for synchronizing clock signals among multiple electronic components using phase synchronous updates. Background technique [0004] The competitive nature and market forces of the integrated circuit (IC) industry tend to encourage the production of digital logic in the most advanced process nodes with the highest available clock speeds. The clock is usually driven by a phase-locked loop (PLL) configured to output a clock signal based on a low-speed device clock signal (often referred to as a "PLL reference clock signal" or sim...

AI Technical Summary

Problems solved by technology

Unfortunately, this approach prevents further SYSREF based phase updates by altering the clock and / or reset signals without interfering with downstream logic

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