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Grinding process for polycrystalline silicon layer and wafer

A grinding process, polysilicon layer technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as affecting wafer quality

Pending Publication Date: 2022-03-01
HEJIAN TECH SUZHOU
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Since these raised defects are randomly distributed on the polysilicon surface, even after polysilicon etching, they cannot be completely reduced, which affects the quality of the entire wafer

Method used

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  • Grinding process for polycrystalline silicon layer and wafer
  • Grinding process for polycrystalline silicon layer and wafer

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Embodiment Construction

[0022] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0023] figure 2 A specific flow of an embodiment of a polishing process for a polysilicon layer according to the present invention is shown. The grinding process generally includes the following steps:

[0024] 1) Measuring wafer thickness

[0025] Obtain the initial thickness D0 of the wafer before grinding.

[0026] 2) Chemical-mechanical polishing of the polysilicon layer of the wafer to obtain a polished surface

[0027] Abraded surfaces with a certain degree of flatness are obtained based on chemical etching and mechanical removal. In this step, technicians can adjust specific grinding parameters according to dif...

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Abstract

The invention discloses a grinding process for a polycrystalline silicon layer. The grinding process comprises the following steps: 1) measuring the thickness of a wafer; 2) performing chemical mechanical grinding on the polycrystalline silicon layer of the wafer to obtain a grinding surface; 3) carrying out RCA cleaning on the grinding surface; 4) polishing and grinding the grinding surface; (5) CPC cleaning is conducted on the grinding face; and 6) measuring the thickness of the wafer again. The grinding process can effectively reduce the bulge defects randomly distributed on the surface of the polycrystalline silicon. The invention also provides a wafer prepared by using the grinding process.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a grinding process for semiconductor devices and a wafer prepared by using the grinding process. Background technique [0002] Chemical mechanical polishing (CMP) is a commonly used surface planarization technology in wafer manufacturing, which uses a combination of chemical etching and mechanical removal to improve the flatness of the wafer surface. The traditional grinding process requires RCA cleaning and CPC cleaning in sequence after chemical mechanical polishing. Among them, the cleaning brushes made of organic materials in the CPC cleaning process will have organic residues in the process of cleaning the polysilicon surface, forming raised defects mainly composed of carbon on the polysilicon surface. Such as figure 1 As shown, there are protruding defects in 10 random wafers, and the average number is greater than 90 grains per wafer. Since these raised defects a...

Claims

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Application Information

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IPC IPC(8): H01L21/306H01L21/304H01L21/66
CPCH01L21/30625H01L21/304H01L22/12
Inventor 姚斯嘉曹雪平
Owner HEJIAN TECH SUZHOU