Data storage method of solid-state memory, data reading method and solid-state memory

Abstract

The invention provides a data storage method of a solid-state memory, a data reading method and a solid-state memory. The data storage method includes: using an LDPC code with a target check matrix to perform error correction code encoding on the data to be stored, and the target check matrix includes at least The core sub-matrix and the sparse sub-matrix; the coded data and regular check bits generated according to the core sub-matrix coding are stored in a preset conventional storage area; the redundant check bits generated according to the sparse sub-matrix coding are stored in a preset Redundant storage area. When data is read, coded data, regular check bits and corresponding redundant check bits are read; the coded data, regular check bits and redundant check bits are spliced ​​to complete decoding. The invention reduces the coding complexity, effectively improves the lifespan of the solid-state memory through the generation of redundant check bits, and proposes an error-correcting code solution for data reading, which improves the storage space utilization and the efficiency of writing and reading. rate.

Description

technical field [0001] The present invention relates to the technical field of data storage, and in particular, to a data storage method of a solid-state memory, a data reading method and a solid-state memory. Background technique [0002] More and more high-capacity flash memory uses 3D NAND technology. 3D QLC (each unit stores 4 bits of information), PLC (each unit stores 5 bits of information) and other new memories generally have the problem that RBER (raw bit error rate, raw bit error rate) increases rapidly with the number of cycling cycles. As a result, its advantage in cost per bit is offset by its severely shortened lifetime. Reducing the code rate of ECC is a possible solution. Compared with the current mainstream LDPC with a length of 4K+ (longer than 4K bytes), an error correction gain of about 50% can be obtained by increasing the code length by about 3%. However, limited by the size of the wordline, the free space of each physical page page is very limited, a...

AI Technical Summary

Problems solved by technology

3D QLC (each unit stores 4 bits of information), PLC (each unit stores 5 bits of information) and other new types of memory generally have the problem that RBER (raw bit error rate, original bit error rate) increases rapidly with the number of cycling cycles. causing its advantage in cost per bit to be offset by its severely shortened lifetime

This method still needs to read two physical pages each time, and the data area does not make full use of the spare area to store some parity bits, resulting in waste of storage space and reducing the flexibility of the ECC strategy

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