Clock synchronization method, device and system

Abstract

The embodiment of the invention provides a clock synchronization method, device and system.The clock synchronization method applied to a programmable device comprises the steps that in response to a received clock synchronization request, a DMA read instruction is generated, a first timestamp currently written in by a virtual machine is read from a DMA memory through the DMA read instruction, and the first timestamp is written in by the virtual machine; and the first timestamp is updated to an internal clock, so that the effect of accurately synchronizing the programmable device and the virtual machine clock is achieved.

Description

technical field [0001] The embodiments of this specification relate to the field of computer technology, and in particular to a clock synchronization method. One or more embodiments of this specification also relate to a clock synchronization device, system, computing device, and computer-readable storage medium. Background technique [0002] Programmable devices, such as Field Programmable Gate Array FPGA, solve the shortage of custom circuits and can be used to design products in various industries. For example, on the basis of programmable devices, a complete computer system, a virtual machine, with complete hardware system functions and running in a completely isolated environment can be created through software simulation. [0003] In some projects, in order to perform time-related tasks, it is necessary to use programmable device time and virtual machine time. For example, in a network diagnosis project, it is necessary to analyze the full link delay from the applica...

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Problems solved by technology

[0004] However, since the time of the virtual machine and the time of the programmable device are not actually synchronized, it brings certain difficulties to the execution of related projects

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