Low-frequency digital-analog hybrid module clock structure and scan chain design method

Abstract

The invention provides a low-frequency digital-analog hybrid module clock structure and a scan chain design method. Wherein all the registers are divided into M groups according to the sequence, and the number of the registers contained in each register group is consistent with the maximum number of the fan-out registers of the driving unit corresponding to the register group; the clock tree structure of each register in each register group adopts a Z-H clock structure; the clock structure among the M groups of registers is specifically as follows: no clock buffer unit is arranged on the common path of the first group of registers, a second clock buffer unit is added on the common path of the second group of registers, two third clock buffer units are added on the common path of the third group of registers, and so on; and (M-1) M-th clock buffer units are added on the common path of the M-th group of registers serving as the last group of registers. According to the invention, the number of registers which are overturned at the same time can be minimized, and the overall power consumption and instantaneous power consumption of the design are reduced.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a low-frequency digital-analog hybrid module clock structure and a scan chain design method. Background technique [0002] During the working process of the low-frequency digital-analog hybrid module, it will be turned on or off according to the needs of the work; if there are too many flip registers at the same time when it is turned on, the instantaneous power consumption will rise, the turn-on voltage will be pulled down, and the module will fail to turn on; if the design is There is an LDO, which will cause LDO oscillation to directly affect the work of the module. In order to avoid this situation, higher requirements are imposed on the power supply module, which increases the design cost or sacrifices part of the design performance. [0003] In the low-frequency digital-analog hybrid module, the analog signal itself does not belong to any clock domain, and...

AI Technical Summary

Problems solved by technology

[0004] In order to solve the problem of excessive instantaneous power consumption caused by too many simultaneously flipped registers in the low-frequency digital-analog hybrid module, the present invention provides a clock structure and scan chain design method for the low-frequency digital-analog hybrid module. The number of flipped registers is minimized, and the timing problems caused by manual clock tree processing are handled by changing the connection order of the scan chains, reducing the overall power consumption and instantaneous power consumption of the design

Images