Electronic package and fabrication method thereof

Abstract

The present invention relates to an electronic package and a method of fabricating the same, including disposing at least one magnetic conductive member between a carrier and an electronic component, the electronic component having a first conductive layer, and the carrier having a second conductive layer such that the magnetic conductive member is located between the first conductive layer and the second conductive layer, and a plurality of conductive bumps electrically connected with the first conductive layer and the second conductive layer are arranged between the electronic component and the bearing part so as to surround the magnetic conductive part to generate magnetic flux.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular to an electronic package with a ferromagnetic material and a manufacturing method thereof. Background technique [0002] In general semiconductor application devices, such as communication or high-frequency semiconductor devices, it is often necessary to electrically connect multiple radio frequency (radio frequency) passive components such as resistors, inductors, capacitors, and oscillators to the packaged semiconductor chip. Thus, the semiconductor chip has a specific current characteristic or emits a signal. [0003] Taking a Ball Grid Array (BGA for short) semiconductor device as an example, although multiple passive components are placed on the surface of the substrate, in order to prevent the passive components from hindering the electrical connection and configuration between the semiconductor chip and the multiple pads, Traditionally, the passive elements are mostly placed...

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Problems solved by technology

[0006] However, the inductance element 12 is chip type, so it requires a large volume, especially the inductance element 12 required by the power circuit, and the inductance element 12 is too far away from the semiconductor chip 11, causing parasitic effects along with the The inductance element 12 is increased away from the semiconductor chip 11, thus causing the electrical performance of the semiconductor package 1 to be poor.

[0007] In addition, the inductance element 12 is formed on the surface of the packaging substrate 10, which will occupy a large amount of layout space of the packaging substrate 10, thus making it difficult for the semiconductor package 1 to meet the miniaturization requirements.

[0008] In addition, the industry also replaces the chip-type inductance element 12 with a coil-type inductance 12', such as figure 1 'shown semiconductor package 1', but the coil-type inductor 12' is only set on the packaging substrate 10, so the analog value of the inductance generated by the coil-type inductor 12' is limited, resulting in the inductance of the coil-type inductor 12' The value is too small to fit the requirement

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