Nonlinearity calibration method of phase interpolator

Abstract

The invention discloses a nonlinearity calibration method for a phase interpolator, and the method comprises the steps: outputting a first sampling clock, and enabling the edge of the first sampling clock to be aligned with the edge of a reference clock; outputting a third sampling clock, and aligning the edge of the third sampling clock with the edge of the reference clock; outputting a first sampling clock, enabling the edge of the first sampling clock to be below the edge of the reference clock, outputting a second sampling clock, enabling the edge of the second sampling clock to be above the edge of the reference clock, and calculating a first difference value of digital signals corresponding to the first sampling clock and the second sampling clock; the phase of the second sampling clock is the average value of the phases of the first sampling clock and the third sampling clock; outputting a second sampling clock, enabling the edge of the second sampling clock to be below the edge of the reference clock, outputting a third sampling clock, enabling the edge of the third sampling clock to be above the edge of the reference clock, and calculating a second difference value of digital signals corresponding to the second sampling clock and the third sampling clock; the second difference value is equal to the first difference value.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to the design of physical layer circuits in high-speed serial interface chips, especially the linearity calibration method of a digital controlled phase interpolator in a clock and data recovery circuit . Background technique [0002] Digitally controlled phase interpolators are usually used in clock and data recovery circuits at the receiving end of high-speed serial interface chips. Its input is usually a quadrature clock signal. According to the difference of the input control number, a multi-phase clock can be generated by interpolation. refer to figure 1 As shown, the basic principle of the phase interpolator can be explained by the following equation: [0003] [0004] [0005] Among them, α and β respectively represent the control codes of the two quadrature clock signals, and sinθ and cosθ represent the two quadrature clock signals. Various phas...

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Problems solved by technology

[0008] In order to avoid the above problems, some circuit design engineers will design some auxiliary circuits in the interface chip to measure the linearity of the phase interpolator, but this method will cause additional load

In addition, under the accuracy of 300 femtoseconds, the error of the measurement circuit needs to be calibrated again and again.

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