Packaging structure and preparation method thereof

Abstract

The invention provides a packaging structure and a preparation method, the packaging structure comprises a lower packaging body, an upper packaging body and a first rewiring stacking layer arranged between the lower packaging body and the upper packaging body, and the first rewiring stacking layer is electrically connected with the lower packaging body and the upper packaging body; the lower packaging body comprises a prefabricated substrate and a first plastic packaging layer surrounding the periphery of the prefabricated substrate; wherein the minimum line width / line distance of the first rewiring stacking layer is smaller than the minimum line width / line distance of the prefabricated substrate. The lower packaging body comprises a prefabricated substrate and a first rewiring stacking layer, the first rewiring stacking layer is arranged above the prefabricated substrate, the minimum line width / line distance of the first rewiring stacking layer is smaller than that of the prefabricated substrate, and more chips and / or device packaging bodies are integrated in the packaging structure through the first rewiring stacking layer with the smaller line width / line distance.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, in particular to a packaging structure and a preparation method thereof. Background technique [0002] The rapid development of high-speed computing and artificial intelligence puts forward higher requirements for the packaging of semiconductor chips and packages. In particular, higher requirements are put forward for packaging substrates, and laminated substrates are usually required to have narrower line width / line spacing and better voltage drop control. The line width / line spacing of traditional laminated substrate wiring is usually around 15um / 15um, which is increasingly unable to meet the high-density packaging requirements of electronic components used in high-speed computing and artificial intelligence. [0003] In addition, the traditional laminated substrate technology has great difficulties in 1) the supply of stacked dielectric materials; 2) the manufacturing cycle; 3...

AI Technical Summary

Problems solved by technology

The line width / line spacing of traditional laminated substrate wiring is usually around 15um / 15um, which is increasingly unable to meet the high-density packaging requirements of electronic components used in high-speed computing and artificial intelligence.

[0003] In addition, the traditional laminated substrate technology has great difficulties in 1) the supply of stacked dielectric materials; 2) the manufacturing cycle; 3) wiring with a line width of less than 10um and the yield control of embedded chips.

[0004] Therefore, it is necessary to propose a new packaging structure and preparation method to overcome the need for high-density packaging due to the wide line width / line spacing of traditional laminated substrates.

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