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Bonding structure of semiconductor package and method of forming same

A bonding structure and packaging technology, which can be used in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., and can solve problems such as limited bonding area

Pending Publication Date: 2022-04-22
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In view of the problems existing in the related art, the object of the present invention is to provide a bonding structure of a semiconductor package and its forming method to solve the problem of the bonding area when the wires in the bonding structure of the semiconductor package are connected to the pads in the circuit board. Limited questions to further increase connection reliability

Method used

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  • Bonding structure of semiconductor package and method of forming same
  • Bonding structure of semiconductor package and method of forming same
  • Bonding structure of semiconductor package and method of forming same

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Embodiment Construction

[0027] The following summary provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which a first component may be formed between the first component and the second component. Additional components such that the first and second components may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purposes of simplicity and clarity and does not in itself indicate a relationship between the...

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Abstract

The embodiment of the invention relates to a bonding structure of a semiconductor package and a method for forming the same. The bonding structure of the semiconductor package includes a lead frame including a first portion and a second portion, a first end portion of the second portion being connected to the first portion. The bonding structure of the semiconductor package further includes an etching impedance layer disposed at a second end portion of the second portion opposite to the first end portion, where a width of the second portion at an intermediate portion between the first end portion and the second end portion is less than a width of the first end portion and less than a width of the second end portion. According to the technical scheme, the problem that the joint area of the lead frame and the circuit board is limited can be solved, so that the connection reliability is improved.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and more particularly, to a bonding structure of a semiconductor package and a forming method thereof. Background technique [0002] In the existing QFN (Quad Flat No-leads Package) structure, when the lead frame (Lead Frame) is arranged on the circuit board (PCB) and is connected with the circuit board, the lower end of the lead frame The exposed pins from the molding compound are planar, and the connection between the circuit board and the lead frame is also planar, which limits the bonding area between the lead frame and the circuit board. The joint area is the main item of the drop test in the Board Level Reliability Test (Board Level Reliability Test). The drop test is used to investigate the reliability of the solder ball joints connecting the package structure and the circuit board. test. Therefore, when the leads of the lead frame and the pads of the circuit board are bon...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/495H01L23/31H01L21/48
CPCH01L23/49541H01L23/49582H01L23/3107H01L21/4828H01L2924/181H01L2924/00012
Inventor 徐志宏黄进吏谢玫璘董明澄林洁莹徐义程陈苑君吴克璞
Owner ADVANCED SEMICON ENG INC
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