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Clock frequency control method and device, equipment and storage medium

A technology of clock frequency and control method, which is applied in the computer field, can solve the problem of low debugging efficiency and achieve the effect of improving debugging efficiency

Active Publication Date: 2022-05-06
LOONGSON TECH CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The embodiment of this application provides a clock frequency control method, device, equipment and storage medium to solve the problem of low debugging efficiency

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  • Clock frequency control method and device, equipment and storage medium
  • Clock frequency control method and device, equipment and storage medium
  • Clock frequency control method and device, equipment and storage medium

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Embodiment Construction

[0029] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this application.

[0030] figure 1 A schematic diagram of a processor architecture provided by an embodiment of the present application. like figure 1 As shown, the processor may include a phase locked loop module 100 , a memory module 200 and an audio module 300 . Wherein, the phase locked loop module 100 may include a configurable frequency divider 110 , a frequency multip...

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Abstract

The invention provides a clock frequency control method and device, equipment and a storage medium. The method comprises the following steps: acquiring a node clock frequency; determining a first frequency division coefficient according to the node clock frequency; wherein the first frequency division coefficient is the frequency division coefficient of the audio module; and writing the first frequency division coefficient into a configuration register of the phase-locked loop module. According to the invention, the first frequency division coefficient can be determined automatically and quickly, so that the working clock frequency provided by the phase-locked loop module to the audio module meets the requirements of the audio module, and the debugging efficiency is improved.

Description

technical field [0001] The present application relates to the field of computer technology, and in particular to a clock frequency control method, device, equipment and storage medium. Background technique [0002] In some processor chips, the working clock signal of the audio module and the working clock signal of the memory module are two clock signals obtained by frequency-dividing the node clock signal by the same PLL (Phase Locked Loop, phase locked loop) module. During the debugging process of the BIOS (Basic Input Output System) program of the above-mentioned processor chip, the staff will often change the configuration parameters of the PLL module to adjust the working clock frequency of the memory module, so as to debug the memory module in Whether it can work normally under various operating clock frequencies. In order to make the audio module work normally, it is necessary to adjust the frequency division coefficient of the audio module in the configuration param...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/08
CPCG06F1/08Y02D10/00
Inventor 苏梦岩袁俊卿
Owner LOONGSON TECH CORP