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Chip interconnection circuit based on TileLink and data transmission method

A data transmission method and data technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of incomplete TileLink bus channel, incomplete bus operation and transmission, etc., and achieve the effect of avoiding bus deadlock

Pending Publication Date: 2022-05-06
JIANGNAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In order to solve the problems of incomplete TileLink bus channel, incomplete bus operation transmission and inability to flexibly configure the circuit structure according to the specific forwarded TileLink bus channel, channel data bit width, and SerDes data transmission bit width in the current cross-chip transmission process, The invention provides a TileLink-based chip interconnection circuit and data transmission method

Method used

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  • Chip interconnection circuit based on TileLink and data transmission method
  • Chip interconnection circuit based on TileLink and data transmission method
  • Chip interconnection circuit based on TileLink and data transmission method

Examples

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Embodiment 1

[0082] This embodiment provides a chip interconnection circuit based on TileLink, the interconnection circuit includes: a sending end and a receiving end; the sending end and the receiving end are respectively set in the first chip and the second chip using the TileLink bus , the first chip is connected to the second chip, and the interconnection circuit implements inter-chip interconnection and data transmission between the first chip and the second chip;

[0083]The sending end includes: a first TileLink serialization and deserialization module, a first Serdes control module; the first TileLink serialization and deserialization module is used to unify the format and serialize the received data from the TileLink bus and send it to The first Serdes control module is also used to recover the serialized data received from the first Serdes control module into data corresponding to the channel of the TileLink bus, and transmit it to the TileLink bus;

[0084] The receiving end inc...

Embodiment 2

[0087] This embodiment provides a chip interconnection circuit based on TileLink, which serially transmits data on several parallel channels of the TileLink bus through SerDes to complete data transmission across chips.

[0088] According to the interconnection architecture of this embodiment such as figure 1 and figure 2 as shown, figure 1 It is a schematic diagram of the chip architecture at the sending end of the inter-chip interconnection circuit, figure 2 It is a schematic diagram of the chip architecture of the receiving end of the inter-chip interconnection circuit; the interconnection architecture of the interconnection architecture includes a sending end and a receiving end. The chip 2 of the bus, the txp of the chip 1 is connected to the rxp of the chip 2, the txn of the chip 1 is connected to the rxn of the chip 2, the rxp of the chip 1 is connected to the txp of the chip 2, The rxn of the chip 1 is connected to the txn of the chip 2 to realize the inter-chip i...

Embodiment 3

[0103] This embodiment provides a chip interconnection data transmission method based on the TileLink bus, which is implemented based on the chip interconnection circuit in Embodiment 2. During the data stream transmission process of the method, when the TileLink buses A, C, and E in the chip 1 When a channel initiates a message, the method includes the steps of:

[0104] Step 1: The channel arbitration module in the chip 1 unifies the data of the three channels A, C, and E of the TileLink bus. The new data format is shown in Table 1, including chanId indicating the channel of the source, and opcode indicating the channel message type , param indicates the parameter code, size indicates the logarithm of the size of the data carried, source indicates the source device ID, address indicates the target address of the operation, data indicates the data carried in the message, corrupt indicates whether the data carried in the message is wrong, and union indicates whether the channel...

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Abstract

The invention discloses a chip interconnection circuit based on TileLink and a data transmission method, and belongs to the technical field of chip interconnection. The interconnection circuit comprises a transmitting end and a receiving end, the transmitting end and the receiving end are respectively arranged in a first chip and a second chip which adopt a TileLink bus, the problem that multi-channel data cross-chip transmission cannot be performed in the prior art can be solved by increasing inter-channel arbitration and unifying the data format of each channel, and a circuit structure can be flexibly configured according to the data width of the TileLink bus; a serialization circuit is configured through parameterization, so that the interconnection circuit can be adapted to SerDes with any interface width; the priority is set in the arbitration circuit, so that the message is prevented from entering a routing loop or resource deadlock in the transmission process of the TileLink bus network, the bus deadlock phenomenon is avoided, and the chip interconnection structure and the data transmission method are greatly optimized.

Description

technical field [0001] The invention relates to a TileLink-based chip interconnection circuit and a data transmission method, belonging to the technical field of chip interconnection. Background technique [0002] In the coming post-Moore era, the advanced chip manufacturing process is gradually approaching the physical limit. On the other hand, the design cost of the advanced process is also rising. In this context, the advantages of dividing the SoC system into multiple chips and then forming an overall solution through inter-chip interconnection are gradually emerging. How to realize the interconnection between chips and the data transmission between chips is one of the important issues. [0003] The TileLink bus is a high-speed, low-latency, high-throughput, scalable on-chip bus designed for RISC-V instruction set CPUs, and is used to connect processor cores, caches, DMAs and other devices. The TileLink bus supports all communication needs from a single peripheral to h...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/36G06F13/42
CPCG06F13/36G06F13/4282G06F2213/36Y02D10/00
Inventor 虞致国洪广伟顾晓峰
Owner JIANGNAN UNIV
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