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Yield testing circuit and method based on low-power-consumption switch pin of memory

A technology for testing circuits and memories, applied in static memories, instruments, climate sustainability, etc., can solve the problems of no research, lack of low-power functional pin test circuits and methods, and reduce expenditures and labor costs Effect

Pending Publication Date: 2022-05-27
四川创安微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The technical problem to be solved by the present invention is that most of the prior art is aimed at the chip read and write function test, but lacks a memory-based low-power functional pin test circuit and method. The purpose of the present invention is to provide a low-power memory-based The yield test circuit and method of the switch pin, the present invention does not study the function test of the low power consumption pin, but from the rigorous meaning and angle, aiming at how to ensure that the low power consumption pin (Low Power Down, LPD) can be normally on Switch between "low level" and "high level", so that its power saving function will not be affected

Method used

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  • Yield testing circuit and method based on low-power-consumption switch pin of memory
  • Yield testing circuit and method based on low-power-consumption switch pin of memory
  • Yield testing circuit and method based on low-power-consumption switch pin of memory

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Embodiment 1

[0050] like Figure 1 to Figure 4 As shown, the present invention is a yield test circuit based on low power consumption switch pins of memory, such as figure 1 As shown, the test circuit includes a DFT mode control module (TDR), an MBIST control module, a system circuit module and a control pin connection module. The DFT mode control module (TDR), the MBIST control module and the system circuit module are controlled by the The pin connection module is correspondingly connected to the corresponding pin of the memory; the control pin connection module includes OR gate OR1, the first selector MUX A, the second selector MUX B, the third selector MUX C, the first D flip-flop (SFF) and a second D flip-flop (SFF);

[0051] The DFT mode control module (TDR) is used to control and set the value of the LPD pin and provide the switching signal ALL_TEST between the modes of the test mode (DFT mode) and the system mode (Function mode);

[0052] The MBIST control module is used to contro...

Embodiment 2

[0091] such as 1 to Figure 4 As shown, the difference between this embodiment and Embodiment 1 is that the present invention further provides a fault problem testing method based on low power consumption switch pins of SRAM memory, and the testing method is applied to the method described in Embodiment 1 based on A yield test circuit of a low-power switch pin of a memory, the test method comprising:

[0092] Test circuit connection and setting: Based on the described yield test circuit based on the low-power switch pin of memory, set the LPD pin and enable signal pin (CEB / WEB / REB) of SRAM memory to high level, so that the SRAM memory is in Power Down mode, and the read / write enable of the memory is set to high level;

[0093] Fault detection: Detect the presence of a fixed fault "0" (SA0) on the low-power pin LPD of the SRAM memory; specifically:

[0094] When ALL_TEST=1, select DFT mode, make MBIST control the memory control signal of the module

[0095] CEB / REB / WEB@MBIST...

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Abstract

The invention discloses a yield test circuit and method based on a memory low-power switch pin, the yield test circuit comprises a DFT mode control module, an MBIST control module, a system circuit module and a control pin connection module, the DFT mode control module is used for controlling and setting the value of an LPD pin and providing a switching signal ALLTEST between a test mode and a system mode; the MBIST control module is used for controlling and providing an enable signal and switching a test mode to an MBIST mode; the test mode comprises an MBIST mode; the system circuit module is used for controlling and providing an enable signal and a value of an LPD pin; and the control pin connection module is used for inserting a test loop according to the test mode generated by the DFT mode control module, the MBIST control module and the system circuit module, and controlling connection and test of corresponding pins of the memory. Normal work of the functional pins of the memory is ensured, and the yield is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuits (ICs), in particular to a yield test circuit and method based on low-power-consumption switch pins of a memory. Background technique [0002] Based on the field of integrated circuit IC, with the gradual update and evolution of its use process, chip power consumption has become a technical problem in most designs, which leads to the design of low power consumption and the market demand for related devices. Especially in the field of testing, there is a particularly important focus on low-power testing. Combining with the device concept, how to realize the low power consumption test of the device will become an increasingly complex problem, and it is also a topic that needs to be improved and solved urgently. SUMMARY OF THE INVENTION [0003] The technical problem to be solved by the present invention is that in the prior art, most of the tests are aimed at chip read and write functi...

Claims

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Application Information

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IPC IPC(8): G11C29/56
CPCG11C29/56G11C29/56008Y02D10/00
Inventor 不公告发明人
Owner 四川创安微电子有限公司