Semiconductor device structure and forming method thereof

Abstract

The invention provides a semiconductor device structure and a forming method thereof. The semiconductor device structure includes: a first source / drain epitaxial feature structure disposed in an NMOS region; a second source / drain epitaxial feature structure disposed in the NMOS region; a first dielectric feature structure disposed between the first source / drain epitaxial feature structure and the second source / drain epitaxial feature structure; a third source / drain epitaxial feature structure disposed in the PMOS region; a second dielectric feature structure disposed between the second source / drain epitaxial feature structure and the third source / drain epitaxial feature structure; and a conductive feature structure disposed over the first source / drain epitaxial feature structure, the second source / drain epitaxial feature structure, the third source / drain epitaxial feature structure, the first dielectric feature structure, and the second dielectric feature structure.

Description

technical field [0001] Embodiments of the present disclosure relate to semiconductor device structures and methods of forming the same. Background technique [0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced several generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (ie, the number of interconnect devices per wafer area) has generally increased, while geometric size (ie, the smallest component (or wire) that can be produced using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling down also increases the complexity of handling and manufacturing ICs. [0003] As geometries decrease, semiconductor devices such as fin field-effect transistors (fin FETs) m...

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Such scaling down also increases the complexity of handling and manufacturing ICs

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