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Planarization method

A planarization method and patterning technology, applied in the field of planarization, can solve problems affecting product performance or yield, and achieve the effect of improving product performance and reducing height difference

Pending Publication Date: 2022-07-08
POWERCHIP SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, even if the planarization is carried out by the chemical mechanical polishing process, due to the impact of the grinding load effect, there will still be a certain degree of height difference between different device regions, which will affect product performance or yield.

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Embodiment Construction

[0053] 1A to 1E It is a cross-sectional view of a planarization process according to an embodiment of the present invention. Figure 1F to remove Figure 1E Sectional view after the part of the contact window in .

[0054] Please refer to Figure 1A , the substrate 100 is provided. The substrate 100 includes a first region R1 and a second region R2. The first region R1 and the second region R2 may be one and the other of the central region and the edge region, respectively. In some embodiments, the center region and the edge region may be located at the center and edge of the chip, respectively. In this embodiment, the first region R1 is taken as an example of a central region, and the second region R2 is taken as an example of an edge region, but the invention is not limited to this. In other embodiments, the first region R1 may be an edge region, and the second region R2 may be a central region. In this embodiment, the central area may be the memory cell area, and the...

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Abstract

The invention discloses a planarization method. The planarization method comprises the following steps. A substrate is provided. The substrate includes a first region and a second region. A material layer is formed on a substrate. A top surface of the material layer of the first region is lower than a top surface of the material layer of the second region. A patterned photoresist layer is formed on the material layer in the first region. The patterned photoresist layer exposes a top surface of the material layer of the second region. The top surface of the patterned photoresist layer is higher than the top surface of the material layer of the second region. A first etching process is performed on the patterned photoresist layer so that the top surface of the patterned photoresist layer and the top surface of the material layer of the second region have substantially the same height. And performing a second etching process on the patterned photoresist layer and the material layer. In the second etching process, the etching rate of the patterned photoresist layer is substantially the same as the etching rate of the material layer.

Description

technical field [0001] The present invention relates to a semiconductor fabrication process, and in particular, to a planarization method. Background technique [0002] In a semiconductor fabrication process, height differences may be generated between different device regions due to factors such as etching loading effects or different pattern densities. At present, the commonly used planarization method is chemical mechanical polishing. However, even if planarization is performed by the chemical mechanical polishing process, due to the influence of the grinding load effect, there will still be a certain degree of height difference between different device regions, thereby affecting product performance or yield. SUMMARY OF THE INVENTION [0003] The present invention provides a planarization method, which can effectively reduce the height difference between different device regions. [0004] The present invention provides a planarization method, which includes the follow...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/3213H01L21/321H01L27/108H10B12/00
CPCH01L21/32135H01L21/32115H10B12/00H01L21/31055H01L21/76819H10B12/34H01L21/7684H01L21/32134H01L21/3212
Inventor 黄彦智
Owner POWERCHIP SEMICON MFG CORP