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Asynchronous event conflict verification method and system oriented to Verilog design

A technology for asynchronous events and verification methods, applied in computer-aided design, computing, instruments, etc., can solve the problems of high conflict harm, blank automatic verification methods for asynchronous event conflicts, and difficulty in finding, so as to improve reliability, solve undetectable and undetectable problems. Locating the effect of large-scale logic design asynchronous event conflict

Pending Publication Date: 2022-07-29
北京轩宇信息技术有限公司
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Problems solved by technology

[0008] The technical problem solved by the present invention is: in view of the large-scale logic design asynchronous event conflict existing in the prior art is very harmful, it is difficult to find through manual testing and experimental means, and the large-scale logic design asynchronous event conflict automatic verification method is still in the blank problem, a Verilog-oriented asynchronous event conflict verification method and system are proposed

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  • Asynchronous event conflict verification method and system oriented to Verilog design
  • Asynchronous event conflict verification method and system oriented to Verilog design
  • Asynchronous event conflict verification method and system oriented to Verilog design

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Embodiment Construction

[0043] An asynchronous event conflict verification method and system for Verilog design, which analyzes large-scale logic design asynchronous event suspected ports through static analysis, models input and output ports through manual analysis, and finally verifies the problem through simulation verification. , and ultimately improve the reliability of large-scale logic design products. The verification system includes:

[0044] Including Verilog language parsing module, basic device identification module, automatic extraction module for suspected asynchronous events, and asynchronous event port confirmation module, including:

[0045] The Verilog language parsing module is aimed at Verilog design projects and gate-level netlist files, and the analysis module is obtained through Verilog language for language analysis; the basic device identification module identifies basic devices for Verilog design projects; the automatic extraction module for suspected asynchronous events auto...

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Abstract

The invention discloses a Verilog design-oriented asynchronous event conflict verification method and system, and the method comprises the steps: analyzing a large-scale logic design asynchronous event suspected port through a static analysis method through a verification system which comprises a Verilog language analysis module, a basic device recognition module, a suspected asynchronous event automatic extraction module and an asynchronous event port confirmation module; an input port and an output port are modeled through a manual analysis method, finally problems are verified through a simulation verification method, and finally the reliability of large-scale logic design products is improved.

Description

technical field [0001] The invention relates to a Verilog design-oriented asynchronous event conflict verification method and system, and belongs to the technical field of asynchronous event conflict automatic verification based on the identification of all circuit structures. Background technique [0002] Large-scale logic design asynchronous events are two time-independent control signals of large-scale logic design, which cooperate to complete a certain task according to a certain sequence. When there is a timing loophole in the design logic, the conflict between the two control signals arriving at a specific timing will lead to the failure of the execution task. This kind of failure is called a large-scale logic design asynchronous event conflict. Large-scale logic design asynchronous event conflict has the following two characteristics: 1. It is difficult to find, and the event must be triggered in a specific time window, and it is not easy to find it in routine experim...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/3308G06F30/327
CPCG06F30/3308G06F30/327
Inventor 孙宇明曾霞江云松于志杰贾春鹏李铀王宏伟唐柳朱倩尤静姚春月童宗挺赵欢田甜
Owner 北京轩宇信息技术有限公司