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Semiconductor wafer and method for manufacturing the same

A semiconductor and wafer technology, applied in the field of semiconductor layer monitoring, can solve problems such as process variation

Pending Publication Date: 2022-07-29
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] One or more of the manufactured layers may have defects due to manufacturing variation

Method used

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  • Semiconductor wafer and method for manufacturing the same
  • Semiconductor wafer and method for manufacturing the same
  • Semiconductor wafer and method for manufacturing the same

Examples

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Embodiment Construction

[0059] The following disclosure provides many different embodiments or examples for implementing different features of the mentioned subject matter. Specific examples of components, configurations, etc. are described below to simplify the present disclosure. Of course, these are only examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include an embodiment between the first feature and the second feature Embodiments in which additional features are formed between them so that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity, and does not in itself represent a relationship between the various embodiments and / ...

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Abstract

The invention discloses a semiconductor wafer and a manufacturing method thereof. The method includes exposing the semiconductor wafer to one or more dopant species to form one or more first implant layers on the semiconductor wafer, testing one or more geometric parameter values of the formed one or more first implant layers, the semiconductor wafer is conditionally exposed to one or more dopant species after testing the one or more geometric parameter values to form one or more additional implant layers on the semiconductor wafer, conditionally forming one or more additional circuit layers on the semiconductor wafer after forming the one or more additional implant layers to form a plurality of functional circuits on the semiconductor wafer, and conditionally testing the semiconductor wafer in a wafer acceptance test step.

Description

technical field [0001] The subject matter described herein is with regard to semiconductor testing, and in particular, semiconductor layer monitoring during the manufacturing process. Background technique [0002] A semiconductor fabrication process includes multiple fabrication steps or processes, each of which contributes to the formation of one or more semiconductor layers. For example, the layers may be formed by doping a portion of a crystalline semiconductor substrate. In addition, one or more layers may be formed by adding, for example, conductive layers, resistive layers, and / or insulating layers on the crystalline semiconductor substrate. [0003] One or more of the fabricated layers may have defects due to manufacturing variation. SUMMARY OF THE INVENTION [0004] According to embodiments of the present disclosure, there is provided a method of fabricating a semiconductor wafer comprising exposing the semiconductor wafer to one or more dopant species to form on...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66
CPCH01L22/30H01L22/34H01L27/1443H01L21/26513H01L22/20H01L22/12H01L21/265H01L22/22
Inventor 谢丰键张庭豪林俊豪郑允玮李国政
Owner TAIWAN SEMICON MFG CO LTD