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Construction of dynamic block size carry skip adders on FPGA in combination with traveling wave carry adders and routable propagation/generation signals

A technology of skip adder and carry adder, which is applied in the field of constructing dynamic block size carry skip adder on FPGA by combining traveling wave carry adder and routable propagation/generated signal, which can solve large-area overhead, lack of architecture support, etc. problems, to achieve the effect of small die size, superior performance advantages, and reduced area overhead

Pending Publication Date: 2022-08-02
EFINIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, doing this in a typical FPGA has a significant area overhead due to the lack of architectural support for these structures

Method used

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  • Construction of dynamic block size carry skip adders on FPGA in combination with traveling wave carry adders and routable propagation/generation signals
  • Construction of dynamic block size carry skip adders on FPGA in combination with traveling wave carry adders and routable propagation/generation signals
  • Construction of dynamic block size carry skip adders on FPGA in combination with traveling wave carry adders and routable propagation/generation signals

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Embodiment Construction

[0029] In the following description, numerous details are set forth to provide a more thorough explanation of the present embodiments. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments.

[0030] This paper describes techniques for creating a class of fast carry-skipping adder structures on FPGAs, compared to ordinary traveling-wave carry adders (RCAs) that use a modified version of the standard hard RCA to drive routing structures with propagating and generating signals. This structure has low area overhead.

[0031] figure 1 One embodiment is shown in which a 4-LUT (four-level look-up table) 104 is decomposed to implement the functions of propagation 110 , generation 108 and summation 106 . In various embodiments, the look-up table is a blo...

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Abstract

The present invention relates to an adder, which is implemented in a field programmable gate array (FPGA). The adder has a first traveling wave carry adder block for least significant bits of the adder. The adder has a plurality of carry skip adder blocks of different block sizes. Each block size is related to a bit width input to the block. A carry skip adder block of different block sizes is used for a plurality of bits of the adder. The adder has a second traveling wave carry adder block for the most significant bits of the adder.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS [0002] This application requires application number 63144875, filed on February 2, 2021, entitled "Building a Dynamic Block Size Carry Skip Adder (DYNAMICBLOCK SIZE CARRY- SKIP ADDER CONSTRUCTION ON FPGAS BY COMBINING RIPPLE CARRYADDERS WITH ROUTABLE PROPAGATE / GENERATE SIGNALS)", which is incorporated herein by reference. Background technique [0003] Addition is common in digital designs, so modern FPGAs have circuits dedicated to this function. Instead of using pure look-up tables (LUTs) to implement addition, FPGAs are often augmented with circuitry dedicated to efficiently implementing adders. Typically, full adders (eg, each with inputs A, B and carry in, output carry and sum) are connected in one of two ways to implement wider adders. [0004] An easy way to implement a wider adder is to directly add a dedicated route from the carry output of a full adder to the carry input of another full adder, which can be used to imp...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/505G06F30/343G06F115/08
CPCG06F7/505G06F30/343G06F2115/08G06F7/506G06F7/501H03K19/17724
Inventor 马塞尔·戈特
Owner EFINIX INC