Cold electron erase in thin film memory transistors

Abstract

A memory transistor has a tunneling dielectric layer and a charge trapping layer between a channel region and a gate electrode, where the charge trapping layer has a conduction band step lower than a low point of a tunneling barrier in the tunneling dielectric layer when a write voltage is applied such that electrons directly tunnel into the charge trapping layer. The conduction band step of the charge trapping layer is located between-1.0 electron volt and 2.3 electron volt. The memory transistor may include a barrier layer between the tunneling dielectric layer and the charge trapping layer, the barrier layer having a conduction band step smaller than a conduction band step of the charge trapping layer.

Description

technical field [0001] The present invention relates to a writing and erasing system in thin film memory transistors. In particular, the present invention utilizes cold electron erasing in a thin film transistor for fast writing and erasing operations, which also provides the additional advantage of achieving high durability. Background technique [0002] U.S. Published Patent No. 2019 / 0006015 ("Harari"), entitled "Capacitively Coupled Nonvolatile Thin-Film Transistor Strings in Three-Dimensional Arrays," published Jan. 3, 2019, discloses thin-film The memory transistors form an Inverted Or Gate (NOR) memory string. Harari's thin-film transistors can be written and erased in 100 nanoseconds (ns) or less, making them suitable for many applications in typical volatile memory devices, such as dynamic random access memory (DRAM) devices. Harari's thin-film memory transistors also have the advantage of a retention time of several minutes, compared to just a few milliseconds in ...

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Problems solved by technology

These interface traps are detrimental to the persistence of memory transistors and may in fact be the main cause of closing the write window

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