A gate-all-around charge
plasma-based dual-material
gate stack nanowire field-effect
transistor, consisting of: an undoped intrinsic
silicon nanowire body whose thickness is smaller than the
Debye length; a source
electrode and a drain
electrode generated in the undoped intrinsic
silicon nanowire body by means of a charge
plasma, wherein the source
electrode and the drain electrode have
metal contacts with a
work function that is less than the sum of the
electron affinity of
silicon and half the
band gap of silicon, and wherein the source electrode and the drain electrode are configured to generate an
electron charge
plasma in the source and drain regions of the silicon nanowire body; a gate structure surrounding the undoped intrinsic silicon nanowire body, wherein the gate structure comprises a dual-material gate containing a first gate
metal material and a second gate
metal material arranged along a length of the silicon nanowire body, and wherein the first gate metal material has a first
work function and the second gate metal material has a second
work function, the difference between the first and second work functions being 0.5
electron volts; and a
gate dielectric layer arranged between the gate structure and the silicon nanowire body, wherein the
gate dielectric layer comprises a
gate stack structure containing a
silicon dioxide layer and a layer of
dielectric material with a high
dielectric constant; the
transistor is configured to provide improved analog performance with reduced short-channel effects and operates without chemical
doping in the source and drain regions.