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Pulse shaping circuit

A pulse and circuit technology, applied in the field of pulse forming circuits

Inactive Publication Date: 2004-05-19
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] This task is solved by the following pulse shaper

Method used

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Examples

Experimental program
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Embodiment Construction

[0023] In the embodiment shown in Fig. 1, there are p-channel MOS field effect transistors working as controllable switches and possibly n-channel MOS field effect transistors working as controllable switches, at the power supply terminal P A buffer circuit is connected between and N and has power supply potentials V and M, respectively. This buffer circuit is constituted by an inverter including a p-channel type MOS field effect transistor 9 and an n-channel type MOS field effect transistor 10 . In this case, the drain terminals of the two transistors 9 and 10 form the output A of the pulse shaping circuit and are coupled to each other. The input E of the pulse shaping circuit is realized by interconnecting the mutually coupled gate terminals of the two transistors 9 and 10 .

[0024] Finally the supply terminals P, N of the inverter are given by the source terminals of the transistors 9 and 10 so that the source terminal of the transistor 9 is connected to the supply potent...

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Abstract

A pulse shaper circuit includes a buffer having an input, an output and a buffer, a first switch, a second switch, a third switch, a fourth switch and the control apparatus using for each switch. A first control pluse determined time (delta t1) is generated when the otputting signal positioned in the buffer appears a first edge, and a second control pluse determined time (delta t2) generated when the second edge appears. The first control pulse changes over the first switch from the ON state to the OFF state and the fourth switch from the OFF state to the ON state. The second control pulse changes over the second switch from the ON state to the OFF state and the third switch from the OFF state to the ON state.

Description

technical field [0001] The present invention relates to pulse forming circuits. Background technique [0002] A frequent problem in digital circuits is so-called glitch edges (short pulses), which occur especially at switching edges of digital signals and which are distorted by oscillations in the positive or negative direction. The causes of this disturbance edge are various and it is therefore very difficult to prevent its occurrence. The function of digital circuits is greatly affected due to the interference edges that occur. Contents of the invention [0003] The object of the present invention is to specify a circuit for eliminating disturbing edges of digital signals. [0004] This task is solved by the pulse former described below. Implementation structures and improvements of the present invention are located in the following text. [0005] The pulse forming circuit of the present invention comprises [0006] an input, an output, and a buffer with two supply ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K5/1252
CPCH03K5/1252H03K5/01
Inventor B·约翰森R·施内德
Owner INFINEON TECH AG