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Method for making semiconductor with channel capacitor

A technology for trench capacitors and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, capacitors, fixed capacitors, etc., can solve problems such as reducing the pass rate, difficult doping, and increasing resistance.

Inactive Publication Date: 2005-06-22
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, when the buried conductive strip 18 cannot fill the diffusion recess 17 to form a void 19, the dopant in the first polysilicon layer 16 is not easy or cannot be diffused into the semiconductor substrate 1
Further, the known technology is prone to disadvantages such as increasing the resistance value and reducing the yield

Method used

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  • Method for making semiconductor with channel capacitor
  • Method for making semiconductor with channel capacitor
  • Method for making semiconductor with channel capacitor

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Embodiment Construction

[0059] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, according to the following Figure 3-1~Figure 4 Combined with a preferred embodiment of the present invention and accompanying drawings, it will be described in detail.

[0060] Figure 3-1 to Figure 3-9 A cross-sectional view of each step of manufacturing a semiconductor with trench capacitance in a preferred embodiment of the present invention is shown respectively.

[0061] refer to Figure 3-1 , first provide a substrate 100 . In a preferred embodiment of the present invention, the substrate is lightly doped with a p-type dopant, such as boron (B). Next, an oxide layer (oxide layer) 104, a stop layer (stop layer) 105 and a hard mask layer (hard mask layer) 106 are formed on the substrate 100, wherein the hard mask layer 106 is used to define the formation of the trench 101 s position. Next, a deep trench 101 is formed in the substrate...

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Abstract

The invention provides a method for manufacturing a semiconductor with trench capacitance, comprising the following steps: forming a trench in a substrate; in the trench, sequentially forming a glass doped layer with a first height and a first The dielectric layer; the n-type dopant in the glass doped layer is diffused out into the substrate by annealing to form a buried plate; the first dielectric layer and the glass doped layer are removed by wet etching; in the trench In the groove, a second dielectric layer and a first conductive layer having a height equal to the first are sequentially formed, and in the groove, the region on the first conductive layer is defined as an upper region; and a U-shaped insulating layer is formed here ; In the upper region, a ring-shaped conductive layer is formed from the bottom of the U-shaped insulating layer; the insulating layer that is not in contact with the ring-shaped conductive layer is removed to form a ring-shaped insulating layer; and a buried conductive band is formed to fill the above-mentioned in the trench. Thus, buried conductive straps with low resistance are formed.

Description

technical field [0001] The present invention relates to a kind of manufacturing method of the semiconductor that has trench (Trench) electric capacity; Especially relate to a kind of use this method to avoid to form gap between the conductive layer of trench capacitance and buried diffusion area, form the trench capacitance with good conductivity semiconductor. Background technique [0002] Picture 1-1 It is shown that trenches having depths are formed at respective positions on a semiconductor substrate. Such as Picture 1-1 As shown, after a mask 2 is formed on a semiconductor substrate 1, such as silicon semiconductor, a deep trench 10 is formed by etching. Figure 1-2 It is shown that a glass film 11 with n-type doping is formed in the lower region of the trench 10 . Such as Figure 1-2 As shown, generally the n-type doped glass film 11 is a glass film doped with arsenic (As), referred to as ASG for short. Figure 1-3 A buried plate 12 is shown formed near the lower...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01G4/00H01L21/02H01L21/283H01L21/31H01L21/3205H01L21/70
Inventor 朱淑卿
Owner WINBOND ELECTRONICS CORP