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Method of integrating storage unit data region and peripheral circuit region in space reducing technology

A peripheral circuit area and storage unit technology, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., and can solve the problems of electrical connection in the array area of ​​storage units, connection of peripheral lines of undisclosed conductor layers, etc.

Inactive Publication Date: 2006-08-16
MACRONIX INT CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] However, in the known pitch reduction processes, there is only a method for reducing the line width and line spacing of the conductor layer (such as the gate) in the memory cell array through the pitch reduction process, and the method for reducing the pitch is not disclosed. How to connect the conductor layer to the peripheral circuit, that is, in the current pitch reduction process related to the memory cell array, there is no effective way to electrically connect the peripheral circuit area to the memory cell array area with the pitch reduction

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  • Method of integrating storage unit data region and peripheral circuit region in space reducing technology
  • Method of integrating storage unit data region and peripheral circuit region in space reducing technology
  • Method of integrating storage unit data region and peripheral circuit region in space reducing technology

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Embodiment Construction

[0019] Figure 1A to Figure 1J Shown is a top view of a manufacturing process for integrating the memory cell array area and the peripheral circuit area in the pitch reduction process of the preferred embodiment of the present invention, Figure 2A to Figure 2J Shown is a cross-sectional view of a manufacturing process for integrating the memory cell array area and the peripheral circuit area in the pitch reduction process according to a preferred embodiment of the present invention. in Figure 2A to Figure 2J depicted as Figure 1A to Figure 1J The cross-sectional view of the structure along the I-I tangent.

[0020] First, please also refer to Figure 1A and Figure 2A , a substrate 100 is provided, wherein a gate dielectric layer 102 , a conductive layer 104 , a stop layer 106 , a sacrificial layer 108 and a patterned mask layer 110 are sequentially formed on the substrate 100 . The material of the gate dielectric layer 102 is, for example, silicon oxide, and the conduct...

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Abstract

A method for integrating the memory unit array region with the peripheral circuit region in gap reducing technology features that a mask layer is formed before the second high-molecular layer is generated in order to cover the substrate and the boundary area of memory unit array region but expose the memory unit array region. As a result, the boundary area can not be etched for realizing the electric connection to peripheral circuit in following steps.

Description

technical field [0001] The present invention relates to a method for reducing the line width and line distance of a memory cell array in a semiconductor device, and in particular relates to a method for integrating the memory cell array area and the peripheral circuit area in the pitch reduction process. Background technique [0002] Under the condition that circuit integration is required to be higher and higher, the design of the size of the entire circuit device is also forced to advance in the direction of continuous reduction in size. However, the line width and line spacing of semiconductor devices are limited by the critical dimension of lithography exposure, so it is difficult to reduce downwards. Therefore, various pitch reduction processes related to reducing line width and line spacing have been proposed. , and using these pitch reduction technologies, the line width and line pitch in semiconductor devices, such as memory cell arrays, can be reduced to one-half of...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/70
Inventor 陈建维
Owner MACRONIX INT CO LTD