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Memory system control method

A control method and storage system technology, applied in the field of memory address control, can solve the problems of DMA controller process efficiency reduction, processing man-hours or processing time increase, etc.

Inactive Publication Date: 2007-08-15
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] In the conventional method as described above, since the clearing of the cache memory is performed every time the data of the DMA transfer data unit is written in the main memory, the process efficiency of the DMA controller is reduced, and processing man-hours or processing may be generated. The problem of increasing time

Method used

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Examples

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no. 1 example

[0030] FIG. 2 shows the general outline of the control method of the first embodiment of the present invention, and is also a flow chart of the process from the start of DMA transfer to the completion of DMA transfer. Next, its operation will be described.

[0031] First, when a DMA transfer request starts, the DMA controller 106 sends a hold signal for a hold operation to bus masters such as the CPU 101 and the bus interface buffer 103 . In response to the hold signal, the CPU 101 and the bus interface buffer 103 return a hold confirmation signal to the DMA controller 106, so that the DMA controller 106 starts DMA transfer (S201). The DMA controller 106 transfers the data to be transferred to the main memory through the I / O 105 to write the data in the main memory (S202). During this period, when all the data transmitted by DMA has been completely transmitted (S203), the DMA controller controls the clearing means so that the clearing is performed on the data that has not bee...

no. 2 example

[0040] Next, a second embodiment of the present invention will be described. FIG. 3 is a flow chart showing the general outline from the start of the DMA transfer to the completion of the DMA transfer according to the present embodiment. Next, its operation will be described.

[0041] First, when DMA transfer starts, the DMA controller 106 sends a hold signal for a hold operation to bus masters such as the CPU 101 and the bus interface buffer 103 . In response to this signal, the CPU 101 and the bus interface buffer 103 return a hold confirmation signal to the DMA controller 106, so that the DMA controller 106 starts DMA transfer (S301). The DMA controller 106 transfers the data to be transferred to the main memory 104 through the I / O 105 to write the data in the main memory 104 (S302). During this period, when all the data transferred by DMA have been completely transferred (S303), or when the amount of data transferred to the main memory 104 by the DMA transfer method reac...

no. 3 example

[0048] Next, a third embodiment of the present invention will be described. In this embodiment, a first-in-first-out (FIFO) memory of a ring buffer is used as the main memory of the cache memory system in the first embodiment. Hereinafter, the main memory 101 in FIG. 1 is regarded as the FIFO memory of the ring buffer. FIG. 5 is a diagram showing the status of addresses in the main memory 104. As shown in FIG. In addition, the control method of this embodiment is similar to that of the first embodiment, and this embodiment is described using the flow charts shown in FIG. 2 , FIG. 1 and FIG. 5 .

[0049] First, DMA transfer starts, and the DMA controller 106 sends a hold signal for a hold operation to bus masters such as the CPU 101 and the bus interface buffer 103 . In response to the hold signal, the CPU 101 and the bus interface buffer 103 return a hold confirmation signal to the DMA controller 106, so that the DMA controller 106 starts DMA transfer (S201). Also, the DMA ...

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Abstract

A memory system control method is a control method in a system which comprises a central processing unit, a cache memory, and a main memory, and has a DMA transfer function to said main memory, wherein when the amount of data transferred to said main memory reaches an arbitrary value, the data in the cache memory corresponding to the address of data in said main memory which have been written by the DMA transfer are purged.

Description

technical field [0001] The present invention relates to memory address control in a processor system having a DMA controller and a main memory, wherein the DMA controller is used to perform DMA control of the cache memory and the main memory. Background technique [0002] Generally, as a method of achieving improvement in processor speed, in order to read data, programs, etc. Near the processor, in order to store part of the data program of the main memory in the cache memory, so as to access the data program at a high speed. [0003] In this cache memory system, part of the data in the main memory is read into the cache memory, so as to control the address of the part of the data stored in the main memory read into the cache memory, so that when the processor reads the desired When storing data, if they exist in the cache memory, desired data can be obtained from the cache memory. Fig. 10 shows the relationship between data in the main memory and data in the cache memory....

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/08G06F13/28G06F12/00
CPCG06F12/0808
Inventor 田村创石田英雄多田纳雅贵
Owner PANASONIC CORP
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