Base station having a hybrid parallel/serial bus interface

A serial bus interface, base station technology, applied in parallel/serial conversion, connection components, radio/induction link selection and arrangement, etc., can solve problems such as increasing bus cost

Inactive Publication Date: 2007-08-15
INTERDIGITAL TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Large number of pins or connections may increase bus cost depending on implementation

Method used

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  • Base station having a hybrid parallel/serial bus interface
  • Base station having a hybrid parallel/serial bus interface
  • Base station having a hybrid parallel/serial bus interface

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0026] FIG. 2 is a block diagram of a hybrid parallel / serial bus interface, and FIG. 3 is a flow chart of data transmission operations of a hybrid parallel / serial bus interface. A data block is transmitted across the interface from node 150 to node 252 (54). A data block demultiplexing device 40 receives the block and demultiplexes it into i small blocks for transmission on i data transmission lines 44 (56). The value i is determined according to the trade-off between the number of connections and the transmission speed. One way to determine the value of i is to first determine a maximum allowable delay in transmitting the data block. According to the maximum delay, the minimum number of lines required to transmit the block can be determined. With a minimum number of wires, the wires used to transmit data are selected to be at least the minimum amount. Lines 44 may be pins and their associated connections on a circuit board or on an IC connection. One way to demultiplex in...

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PUM

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Abstract

A hybrid serial / parallel bus interface for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.

Description

technical field [0001] The present invention relates to bus data transfer. In particular, the present invention is directed to reducing wires for transferring bus data. Background technique [0002] Figure 1 is an example of a bus used to transmit data. 1 is an illustration of receive and transmit gain controllers (GC) 30, 32, and a GC controller 38 for a wireless communication system. A communication station, such as a base station or user equipment, transmits (TX) and receives (RX) signals. To control these signal gains, which fall within the operating range of other receive / transmit components, the GC 30, 32 adjusts the degree of gain on the RX and TX signals. [0003] To control the gain parameters of the GCs 30, 32, a GC controller 38 is utilized. That is, as shown in FIG. 1 , the GC controller 38 uses a power control bus, such as 16 line buses 34 and 36 to send the gain values ​​of the TX36 and RX34 signals, such as eight lines each. Power control bus lines 34, 36...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/14G06F13/38H04L29/00F16BG06F13/00G06F13/40H03M9/00H04W88/08H04W92/00
CPCG06F13/4009
Inventor 约瑟·葛瑞丹艾佛瑞·史达福利提摩西·A·亚瑟尼司
Owner INTERDIGITAL TECH CORP
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