Integrated storage with storage unit having magnetic resistance storage effect

Abstract

The present invention relates to an integrated memory comprising memory cells (MC) with magneto-resistive memory effect, which is each connected between one column line (Blo to BLn) and one row line (Wlo to WLm). The row lines (WL2) are connectable with a terminal for a selection-signal (Gno) to read out a data signal (DA) from one of the memory cells (MC3), or to write a data signal (DA) in one of the memory cells (MC3) through the column line (BL2) connected with the memory cell (MC3). One or more column lines (Blo to BLn) not connected with the memory cell (MC3) are so controllable that, to read or write the data signals (DA), they are electrically isolated in the read amplifier (3). Therefore, in case of an existing faulty memory cell (MC2), it is possible to orderly read or write the data-signals (DA) of the memory cell (MC3).

Description

technical field [0001] The present invention relates to an integrated memory whose memory cells have a magnetoresistive memory effect, said memory cells are respectively connected between one of a plurality of column lines and one of a plurality of row lines, wherein said column The line is connected to the sense amplifier, and the row line can be connected to the terminal of the selection signal, so as to read the data signal of one of the memory cells through the column line connected to the memory cell, or write data to one of the memory cells Signal. Background technique [0002] In order to store data signals, memory cells with a magnetoresistive memory effect usually have a state-variable ferromagnetic layer. This memory effect is generally known as the so-called GMR (giant magnetoresistance) effect or TMR (tunnel magnetoresistance) effect. Here, the resistance of such memory cells depends on the magnetization in the ferromagnetic layer. [0003] Memories with memor...

AI Technical Summary

Problems solved by technology

The short also affects other memory cells along that column or row line

In addition, in the functional test, due to a short circuit of a memory cell, it will not be possible to test other memory cells along the relevant line.

When repairing a memory with damaged memory cells, this problem cannot be overcome by replacing a single associated row or column line, since the short would still interfere with the function of the memory cell of other associated lines

In addition, the remaining short can cause parasitic currents on other lines, which can adversely affect the read or write process

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