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Method and apparatus for improving capture and lock characteristics of phase lock loops

A phase-locked loop and phase technology, applied in the field of phase-locked loops, can solve the problems of complex calculation process and insufficient application

Inactive Publication Date: 2002-07-10
GENERAL ELECTRIC CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Phase-locked loops can use such an error signal to improve the characteristics of the phase-locked loop, but these methods are computationally complex, need to be improved, and are not robust enough for specific applications

Method used

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  • Method and apparatus for improving capture and lock characteristics of phase lock loops
  • Method and apparatus for improving capture and lock characteristics of phase lock loops
  • Method and apparatus for improving capture and lock characteristics of phase lock loops

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Embodiment Construction

[0013] now refer to figure 1 , which shows a dual-phase PLL suitable for the present invention. The demodulator 10 is adapted to receive input signals Vcos and Vsin, which are sinusoidal voltage signals that are approximately 90 degrees out of phase with each other. The demodulator 10 also receives cosine and sine phase signals from a feedback loop, as will be described in detail below. On the basis of these input signals, the demodulator 10 generates an error signal ed, which in a conventional phase-locked loop is defined as:

[0014] Ed=Vcos*Cos(phase)+Vsin*Sin(phase) (1)

[0015] This means that the demodulator 10 generates the sum of these products and outputs the result as an error signal ed. Signal ed is then processed in two separate parallel paths. In the proportional path, the error signal ed is fed to an amplifier 12 which linearly amplifies this error signal ed by a factor of amplification Kp. Kp is usually set to make this loop obtain the required bandwidth. ...

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Abstract

A phase lock loop with an improved capture and lock characteristics. A first displacement error signal, a quadrature error signal, and a second displacement error signal arc generated, the second displacement error signal combining the benefits of the first displacement error signal and the quadrature error signal to more closely approximate an ideal error signal and avoid false lock.

Description

Background of the invention [0001] The present invention generally relates to phase locked loops. In particular, the present invention relates to methods and apparatus for improving the acquisition and phase locking characteristics of dual phase phase locked loops. [0002] A phase-locked loop (PLL) is a circuit that can effectively lock the phase of an input signal to a reference signal. The traditional PLL can be regarded as a kind of non-inductive tunable active filter with adjustable bandwidth. When the phase difference between the reference signal and the input signal is a constant, the PLL is locked. If either the input signal or the reference signal changes phase, a phase detector in the middle of the PLL generates an error signal proportional to the magnitude and polarity of the phase change. This error signal causes the phase of the reference signal to change, thereby achieving lock again. PLLs are used in a wide variety of applications including FM radio demodula...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/06H03L7/085H03L7/087H03L7/093H03L7/10H04L7/033
CPCH03L7/093H03L7/085H03L7/087H03L7/10H03L7/08
Inventor W·R·佩尔森
Owner GENERAL ELECTRIC CO