Method and apparatus for improving capture and lock characteristics of phase lock loops
A phase-locked loop and phase technology, applied in the field of phase-locked loops, can solve the problems of complex calculation process and insufficient application
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[0013] now refer to figure 1 , which shows a dual-phase PLL suitable for the present invention. The demodulator 10 is adapted to receive input signals Vcos and Vsin, which are sinusoidal voltage signals that are approximately 90 degrees out of phase with each other. The demodulator 10 also receives cosine and sine phase signals from a feedback loop, as will be described in detail below. On the basis of these input signals, the demodulator 10 generates an error signal ed, which in a conventional phase-locked loop is defined as:
[0014] Ed=Vcos*Cos(phase)+Vsin*Sin(phase) (1)
[0015] This means that the demodulator 10 generates the sum of these products and outputs the result as an error signal ed. Signal ed is then processed in two separate parallel paths. In the proportional path, the error signal ed is fed to an amplifier 12 which linearly amplifies this error signal ed by a factor of amplification Kp. Kp is usually set to make this loop obtain the required bandwidth. ...
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