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Memory controller which increases bus utilization by reordering memory requests

A memory controller and reordering technology, applied in the field of computing systems, can solve problems such as slowing down the access speed

Inactive Publication Date: 2002-12-04
INFINEON TECH AG
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

While allowing for faster and more efficient memory accesses, the complexity required by conventional memory controllers when dealing with multi-bank type storage devices actually slows down the overall access speed of the entire system

Method used

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  • Memory controller which increases bus utilization by reordering memory requests
  • Memory controller which increases bus utilization by reordering memory requests
  • Memory controller which increases bus utilization by reordering memory requests

Examples

Experimental program
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Embodiment Construction

 [0045] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

 [0046] In systems with several devices, such as processors, sharing common resources, various methods have been used to avoid conflicts when more than one device requests access to shared resources. One approach is to resolve conflicts by sequentially operating the processor and by using a time-sharing processor. At this point, in order to avoid conflicts, the processor simply accesses the shared resources "in turn". Such systems that are commonly used include "passing bells" or "marking systems," in which the potentially conflicting processors are simply polled by the system in the same order as the pass bells for a group of users.

 [0047] Unfortunately, the use of sequential processor access methods typically imposes significant limitations on the overall computer system due to the actual amount of time spent polling the competing processor.

 [0048] Another traditional approach to avoiding conflict is to rely on the establish...

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PUM

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Abstract

A scheduler (1006) suitable for reordering memory requests to achieve higher average utilization of the instruction bus (912) and data bus (914) is described. A scheduler (1006) for scheduling a plurality of instructions with respect to a memory (908) comprising M memory banks and a plurality of N memory pages; including a constraint circuit (1016) based at least in part on instructions corresponding to the same memory bank The access delay of other instructions, determine the earliest issue time of each instruction; and include a reordering circuit (1018), determine that the instruction is transmitted to the corresponding, about the earliest issue time of each related instruction and the data occurrence time of the selected instruction Sequence of memory (908).

Description

Background of the invention [0001] The present invention generally relates to computing systems. More specifically, the present invention relates to accessing shared resources within a computing system, such as a multi-processor computer system or the like. Still further, the present invention describes apparatus and methods for reordering storage requests to achieve higher utilization of instructions and data buses.Background of the invention [0002] In a basic computer system, a central processing unit or CPU operates in accordance with a predetermined program or set of instructions stored in a corresponding memory, in addition to the storage processor being provided with a set of instructions or programs running thereon. Storage space in the processor memory or associated additional memory to facilitate processing by the central processing unit during processing. Based on which processor is used to execute the program, the additional memory is used as a memory and temporary inform...

Claims

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Application Information

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IPC IPC(8): G06F12/06G06F12/00G06F12/02G06F13/16
CPCG06F12/0215G06F13/1605G06F13/1621G06F13/1626G06F13/18
Inventor H·斯特拉科夫斯基P·斯扎贝尔斯基
Owner INFINEON TECH AG
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