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Decimal frequency-dividing synthesizer with sinusoidal generator

A technology of fractional frequency division and frequency synthesizer, which is applied in the direction of automatic power control and electrical components, and can solve problems such as interval error and timing error

Inactive Publication Date: 2003-07-30
NOKIA TECHNOLOGLES OY
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Fractional spurious frequencies can also originate from spacing or timing errors of the multimode prescaler

Method used

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  • Decimal frequency-dividing synthesizer with sinusoidal generator
  • Decimal frequency-dividing synthesizer with sinusoidal generator
  • Decimal frequency-dividing synthesizer with sinusoidal generator

Examples

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Embodiment Construction

[0033] best practice

[0034] See now the attached drawings and consider first figure 1, a schematic functional block diagram of a typical delta-sigma modulator based on a fractional phase-locked loop frequency synthesizer is illustrated there and generally designated as 10. The fractional delta-sigma frequency synthesizer 10 includes a phase frequency detector (PFD) 16 , a loop filter 22 , and a voltage controlled oscillator (VCO) 28 . A reference frequency to frequency synthesizer 10 at input 12 is used at input 14 of PFD 16 . Multimode frequency divider 34 is located between VCO output 30 and input 38 of PFD 16 . Output 18 of PFD 16 is coupled to input 20 of loop filter 22 . Loop filter 22 functionally operates as an integrating capacitor. An output 24 of loop filter 22 is coupled to a VCO input 26 . VCO 28 produces a frequency signal at VCO output 30 in response to a signal at its input 26 . The frequency Fout at the VCO output 30 is coupled to the input 32 of a mult...

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PUM

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Abstract

A fractional-N frequency synthesizer is disclosed wherein the multi-modulus frequency divider in the feedback path of the phase locked loop is controlled by a delta-sigma modulator to achieve the desired division ratio. The fractional input control signal to the delta sigma modulator is dithered to break any periodicity in the modulator output signal to avoid the generation of fractional spurious frequencies.

Description

technical field [0001] The present invention relates generally to delta-sigma modulators based on fractional frequency phase-locked loop frequency synthesizers and more particularly to a method of interrupting the period of the delta-sigma modulator output with a sine wave generator to eliminate the generation of fractional spurious frequencies to process a delta-sigma modulator based on a fractional PLL frequency synthesizer. Background of the invention [0002] Digital frequency synthesizers have been used in communication systems for a long time, especially in radio frequency communication systems, where they are used to generate radio frequency signals carried by radio frequency channels. In frequency synthesis, it is desirable to complete the selected frequency output in the shortest possible time while all spurious outputs are minimized. It is well known that a frequency synthesizer can be created by inserting a frequency divider function between the output of a volta...

Claims

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Application Information

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IPC IPC(8): H03L7/197
CPCH03L7/1976H03L7/1978
Inventor J·P·帕塔纳
Owner NOKIA TECHNOLOGLES OY
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