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Method for forming wiring structure

A wiring structure and wiring groove technology, which is applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve problems such as surface cracks and cracks, and achieve the effect of preventing the deterioration of electromigration resistance

Inactive Publication Date: 2004-01-14
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] However, in the conventional example, once the CMP step in the wiring formation process [refer to Figure 13 (d)] carry out annealing for copper film 49 after, as Figure 14 As shown, for example, there is a problem that surface defects such as surface cracks 51 and fissures 52 occur on the surface of the copper film 49 buried in the recess 46.

Method used

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Examples

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Embodiment 1

[0055] Hereinafter, a method of manufacturing an electronic device according to Embodiment 1 of the present invention will be described with reference to the drawings. The present embodiment is characterized in that the Cu film is annealed between the CMP process of the copper (Cu) film as the wiring and the CMP process of the barrier film.

[0056] figure 1 ˜ FIG. 7 are cross-sectional views showing each step of the method of manufacturing the electronic device according to the first embodiment.

[0057] First, if figure 1 As shown, for example, after forming the lower wiring layer 102 inside the insulating film 101 deposited on a semiconductor substrate (not shown), the surface of the insulating film 101 buried in the lower wiring layer 102 is planarized. Then, on the planarized insulating film 101 and the lower wiring layer 102, for example, SiN film 103, SiO 2 film 104 and FSG film 105.

[0058] Then as figure 2 As shown, the SiN film 103, SiO 2 Recesses 106 and w...

Embodiment 2

[0079] Hereinafter, a method of manufacturing an electronic device according to Embodiment 2 of the present invention will be described with reference to the drawings. The present embodiment is characterized in that the CMP (Cu-CMP) process of the Cu film serving as wiring is performed twice, and at the same time, the Cu film is annealed between the Cu-CMP processes.

[0080] Figure 10 (a)-(d) are sectional views which show each process of the manufacturing method of the electronic device of Example 2.

[0081] First, with Example 1 (refer to Figure 1~3 ) same as Figure 10 As shown in (a), for example, after forming the lower wiring layer 102 inside the insulating film 101 deposited on a semiconductor substrate (not shown), the surface of the insulating film 101 buried in the lower wiring layer 102 is planarized. Then, on the planarized insulating film 101 and the lower wiring layer 102, for example, SiN film 103, SiO, and SiO are sequentially deposited by CVD. 2 film 1...

Embodiment 3

[0093] Hereinafter, a method of manufacturing an electronic device according to Embodiment 3 of the present invention will be described with reference to the drawings. The present embodiment is characterized in that after the CMP process for the Cu film and the barrier film as wirings, the Cu film is annealed, and thereafter, at least one CMP process capable of shaving off the Cu film is performed.

[0094] Figure 11 (a)-(d) are sectional views which show each process of the manufacturing method of the electronic device of Example 3.

[0095] First, with Example 1 (refer to Figure 1~3 ) same as Figure 11 As shown in (a), for example, after forming the lower wiring layer 102 inside the insulating film 101 deposited on a semiconductor substrate (not shown), the surface of the insulating film 101 buried in the lower wiring layer 102 is planarized. Then, on the planarized insulating film 101 and the lower wiring layer 102, for example, SiN film 103, SiO 2 film 104 and FSG f...

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Abstract

A recess is formed in an insulating film, and then a conductive film is deposited over the insulating film so as to fill the recess. Thereafter, a heat treatment is performed on the conductive film. Subsequently, the conductive film is partly removed both before and after the step of performing the heat treatment.

Description

technical field [0001] The present invention relates to a method of forming a wiring structure in electronic devices such as semiconductor devices. Background technique [0002] As a conventional method of forming a wiring structure, there is a conventional example in which annealing is performed after a CMP (chemical mechanical polishing) process (for example, refer to JP-A-11-186261). Hereinafter, the wiring forming method of this conventional example will be described with reference to the drawings, taking a case where wiring is formed in a wiring groove formed in an insulating film as an example. [0003] Figure 13 (a)-(e) are sectional views which show each process of the formation method of the wiring structure of a conventional example. [0004] first as Figure 13 As shown in (a), the underlying oxide film 12 is deposited on the silicon substrate 11 by plasma CVD (chemical vapor deposition), and then the SiN film 13 and [0005] first as Figure 13 As shown in (a)...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/321H01L21/768
CPCH01L21/76807H01L21/76838H01L21/76877H01L21/7684H01L2221/1036H01L21/3212
Inventor 原田刚史
Owner PANASONIC CORP
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