Semiconductor device

Abstract

In a ferroelectric storage device, the influences of lower electrodes (111a and 111b) constituting ferroelectric capacitors (110a1-110a3 and 110b1-110b3) and the thermal stresses of the electrodes (111a and 111b) on a ferroelectric layer (113) formed on the electrodes (111a and 111b) can be relieved and, as a result, the disconnection of wires (106a1, 106a2, etc.) connected to the elect rodes (111a and 111b) due to the thermal stresses of the electrodes (111a and 111b) or the characteristic fluctuation or variation of the ferroelectric capacitors (110a1-110a3 and 110b1-110b3) due to the thermal stresses of the electrodes (111a and 111b) applied to the ferroelectric layer (113) are suppressed. The electrodes (111a and 111b) are bent at a plurality of points so that the electrodes can have zigzag planar shapes and divided into pluralities of wiring sections (111a1 and 111a2 and 111b1 and 111b2).

Description

[0001] This application is a divisional application of Chinese patent application 97190579.7 with a filing date of April 18, 1997. technical field [0002] The present invention relates to a semiconductor device, and more particularly, to a configuration for suppressing performance deterioration or reliability reduction caused by thermal stress generated inside its constituent members. Background technique [0003] Conventionally, some semiconductor devices have multilayer wirings, and in such semiconductor devices, lower layer wirings and upper layer wirings are electrically connected through contact holes formed in an interlayer insulating film. [0004] FIG. 13 is an explanatory diagram for explaining the wiring structure in such a semiconductor device, FIG. 13(a) is a plan view, and FIG. 13(b) is a cross-sectional view along line XIIIb-XIIIb thereof. In the figure, 250 is a wiring structure already formed on the silicon substrate 5 . This wiring structure 250 has a lowe...

AI Technical Summary

Problems solved by technology

[0023] However, as shown in the conventional semiconductor device shown in FIG. 13, if the lower layer wiring 1 in the multilayer structure is made of a conductive material with a large thermal expansion coefficient such as platinum, the lower layer wiring 1 formed by a high-temperature process is Shrinkage is carried out at room temperature, so the result will be that a large tension is applied to the upper layer wiring 2a, 2b connected to it.

Especially in the case where the planar shape of the above-mentioned lower-layer wiring 1 is elongated, the thermal stress on the lower-layer wiring 1 applied to the connection portion between the above-mentioned upper-layer wiring 2a, 2b will become very large, and there is a problem in the lower-layer wiring 1. There is a risk of disconnection at the connection portion between wiring 1 and upper-layer wiring 2a, 2b, or upper-layer wiring 2a, 2b

There is such a problem that the thermal stress generated on the above-mentioned lower layer wiring 1 will become an obstacle in obtaining high reliability in the semiconductor device.

[0024] In addition, even in the ferroelectric device to which the conventional ferroelectric capacitors shown in FIGS. The thermal stress of the lower electrode 211 on the connection portion between 206b will become very large, and there will be a disconnection at the connection portion between the lower layer wiring 211 and the upper layer wiring 206a, 206b, or the upper layer wiring 206a, 206b Hazard of disconnection

In addition, in the ferroelectric memory device, in addition to the problem of lower reliability due to disconnection as described above, there is also a problem that the thermal stress of the lower electrode 211 also affects the upper ferroelectric layer 213. Due to this effect, the characteristics of the ferroelectric capacitor may vary and the characteristics may deteriorate, which will lead to a decrease in the performance or reliability of the ferroelectric memory device.

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