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Clocks synchronizer and method with multi-equipment of different clocks

A clock synchronization and clock technology, applied in the direction of generating/distributing signals, pulse technology, instruments, etc., can solve the problems of optimal performance degradation, slow performance, etc.

Inactive Publication Date: 2004-04-07
LG ELECTRONICS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, prior art methods for synchronizing clocks between two devices with different clocks suffer from the problem that the optimal performance of a device with a fast clock speed degrades to the performance of a device with a slow clock speed

Method used

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  • Clocks synchronizer and method with multi-equipment of different clocks
  • Clocks synchronizer and method with multi-equipment of different clocks
  • Clocks synchronizer and method with multi-equipment of different clocks

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Embodiment Construction

[0019] FIG. 1 shows the configuration of a clock synchronization apparatus for devices using different clocks according to a preferred embodiment of the present invention. Fig. 1 has described a kind of clock synchronizing device of the equipment with different clocks, comprises: microprocessor 10, it operates according to 50MHz clock, and generates RAM control signal according to twice of 50MHz; Clock driver 30, it is used for 50MHz clock Double frequency to generate 100MHz clock, and compensate phase difference due to propagation delay between 50MHz clock and 100MHz clock; RAM 20, which operates according to 100MHz clock, and uses two clock cycles of 100MHz clock as operation latency. Here, two clock periods of the 100MHz clock represent two ticks of the 100MHz clock.

[0020] Microprocessor 10 includes a memory controller (not shown in FIG. 1 ), wherein the RAM control signal generation method can be programmed by the user. The storage controller can be a UPM (User Program...

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Abstract

A clock-synchronizing apparatus and method of devices with different clocks are disclosed. Between a first device operated with a first clock and a second device operated with a second clock faster than the first clock, an operation latency of the second device refers to the first clock, control signals that controls the second device are generated at the second clock speed according to the operation latency, and an enable interval of the control signals has a clock period of the first clock. Accordingly, since the first device and the second device can transmit and receive a data to and from each other while being operated by using their own clock, an access latency for the first device to access the second device can be reduced and a transmission band width between the two devices can be effectively used.

Description

technical field [0001] The present invention relates to clock synchronization devices employing different clocks, and in particular to devices and methods for synchronizing two devices employing different operating clocks (hereinafter referred to as 'clocks'). Background technique [0002] Generally speaking, when the clock ratio of RAM (such as SDRAM (Synchronous Dynamic Random Access Memory)) to the memory controller of the microprocessor is 2:1, the clock speed of the RAM is adjusted to slow down and have the same speed as the microprocessor. Processors with the same clock speed. This helps to synchronize the clock ratio to 1:1 regardless of the interface between the synchronizing devices. [0003] If the clocks of each connected device are inconsistent with each other, the clock of the device with the fast clock speed must be slowed down to the level of the clock of the device with the slow clock speed for connection. Therefore, prior art methods for synchronizing cloc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03K19/00G06F1/12G06F19/00H03K23/00
CPCG06F1/12H03K19/00
Inventor 金映锡
Owner LG ELECTRONICS INC