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Active matrix display device

An active matrix and display device technology, applied in optics, instruments, electrical components, etc., can solve problems such as failure to achieve electrical characteristics, overloading of ion implanters or plasma doping machines, pollution, etc.

Inactive Publication Date: 2004-06-16
SEMICON ENERGY LAB CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0016] Second, the existence of the threshold current flowing through the junction between the channel region 412 and the drain region 416 cannot be ignored
[0017] Third, since the mobility of the implanted boron ions is undesirable, some boron ions are inevitably doped into the channel region 412, so that basic electrical characteristics cannot be realized at all, or often cannot be realized.
[0018] Fourth, the high dopant ion implantation required for the process step shown in Figure 4(D) would overload the ion implanter or plasma dopant
cause various problems in these equipment due to contamination and its maintenance
[0019] The fifth problem is that implanting ions with high doping levels may lead to longer process times
[0020] The sixth problem occurs when annealing with laser
In this case, the effect of laser annealing is also very different between the two groups of regions, which is disadvantageous
There will be a big difference in the electrical characteristics between the n-channel thin film transistor and the p-channel thin film transistor shown on the left and right of Figure 4(D)

Method used

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Examples

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Effect test

no. 1 example

[0050] Figure 1(A)-1(E), Figure 2(A)-2(D) and Figure 3(A)-3(B) Process steps for manufacturing a thin film transistor according to a first embodiment in which a CMOS structure is formed with a thin film transistor formed on a glass substrate are shown.

[0051] First, as shown in FIG. 1(A), a silicon oxide film 102 constituting an underlying layer is formed on a glass substrate 101 . The silicon oxide film 102 is grown to a thickness of about 3000 angstroms by a suitable technique such as sputtering or plasma chemical vapor deposition (CVD). For example, a Corning 7059 or Corning 1737 glass plate can be used as the glass substrate 101 . In addition, a quartz substrate with high heat resistance can also be used as the light-transmitting substrate, although this substrate is expensive.

[0052] After the silicon oxide film 102 is formed, a silicon thin film for later forming an active layer of a thin film transistor is formed. In this embodiment, first, a 500 angstrom thic...

no. 2 example

[0091] The second embodiment of the present invention provides a thin film transistor CMOS structure, wherein the offset gate region is only formed in the n-channel thin film transistor. Unlike the offset gate region described in the first embodiment, the offset gate region of this embodiment is formed of an anodized film of a porous structure. (In the first example, the offset gate region was formed using a final remaining anodized film having a fine and dense structure.)

[0092] Similar to the low doping concentration region, a typical example is the LDD region, and the offset gate region has the following functions:

[0093] Reduce cut-off current;

[0094] Increase the resistance between the source and the drain, thereby reducing the mobility of the current-carrying holes of the n-channel thin film transistor;

[0095] Prevents TFT degradation caused by hot carriers.

[0096] Figure 5(A)-5(D) Process steps of the method for manufacturing a thin film transistor circui...

no. 3 example

[0108] The third embodiment of the present invention is a modification of the first embodiment. Specifically, the doping process shown in FIG. 2(B) for implanting phosphorus ions and the doping process shown in FIG. 2(C) for implanting boron ions are performed in reverse order. However, it is clear that the third embodiment has the same advantages as the first embodiment, which means that the concentration of phosphorus ions and boron ions can be controlled separately.

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Abstract

In a circuit configuration comprising an n-channel thin-film transistor and a p-channel thin-film transistor integrally produced on a single substrate, a lightly-doped drain (LDD) region is formed selectively in the n-channel thin-film transistor, and damages to semiconductor layers caused when implanting impurity ions are balanced between the n- and p-channel thin-film transistors. This configuration achieves a balance between the n- and p-channel thin-film transistors and thereby provides high characteristics CMOS circuit.

Description

[0001] This application is a divisional application of the original application with the application number 99102192.4 and the filing date of February 9, 1997. The earlier application of the original application is JP96-48272, and the earlier application date is February 9, 1996. technical field [0002] The present invention relates to the structure of a semiconductor device and its manufacturing method, wherein p-channel and n-channel thin film transistors are formed on the same substrate. In particular, the present invention relates to circuit structures of complementary metallization semiconductor (CMOS) devices including thin film transistors disposed on glass substrates and methods of manufacturing the same. Background technique [0003] In one conventional technique used to fabricate thin film transistors, a silicon layer is formed on a glass substrate, and the silicon layer is used to fabricate thin film transistors. At present, most manufacturers of active matrix li...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/085H01L21/77H01L21/84H01L27/12H01L29/786
CPCH01L27/1214H01L27/12H01L29/78621H01L27/1222H01L27/127H01L2029/7863H01L27/085
Inventor 山崎舜平福永健司
Owner SEMICON ENERGY LAB CO LTD