Layered power source noise monitoring device of ultra large scale integrated circuit and system

Abstract

A hierarchical power supply noise monitoring device and system for very large scale integrated circuits. The noise-monitoring device is fabricated on-chip to measure the noise on the chip. The noise-monitoring system comprises a plurality of on-chip noise-monitoring devices distributed strategically across the chip. A noise-analysis algorithm analyzes the noise characteristics from the noise data collected from the noise-monitoring devices, and a hierarchical noise-monitoring system maps the noise of each core to the system on chip.

Description

technical field [0001] The present invention relates generally to hierarchical power supply noise monitoring devices and systems for VLSI. This noise monitoring device is fabricated on-chip to measure the noise on the chip. The noise monitoring system includes a plurality of on-chip noise monitoring devices distributed in various key places on the chip. A noise analysis algorithm analyzes noise characteristics based on the noise data collected by these noise monitoring devices, and a hierarchical noise monitoring system maps the noise of each core (core) to the system-on-chip. Background technique [0002] The advent of deep sub-micron technology has brought noise and signal integrity issues into focus. The issue of noise immunity is arguably more important than other metrics such as area, timing, and power, because it doesn't matter how small, fast, or consumes little power if a circuit is faulty . Therefore, to maintain signal integrity, each circuit must have an inher...

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Problems solved by technology

[0006] Unfortunately, the time resolution of the noise measurement is limited by the use of a clock within the sampling circuit

Using a voltage comparator may also cause an unreliable reference voltage due to the additional voltage drop

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