Semiconductor memory device

Abstract

A dummy bit line is provided between a pair of bit lines. The pair of bit lines is set at a power supply voltage and the dummy bit line is set at a ground voltage, and then the pair of bit lines and the dummy bit line are equalized. When a word line is activated in subsequent read operation, the pair of bit lines is at an intermediate potential lower than the power supply voltage, so that an apparent current drive capability of an access transistor decreases, and the static noise margin of a memory cell increases.

Description

technical field [0001] The present invention relates to semiconductor memory devices, and more particularly to SRAM (static random access memory). Background technique [0002] In recent years, with the miniaturization of semiconductor process methods, variations in transistor characteristics have been increasing. Since this variation in characteristics greatly affects the yield of circuits, designing to suppress variation in transistor characteristics will become more and more important in the future. [0003] Conventionally, a CMOS type SRAM memory cell having six transistors is known. It is composed of 1 pair of NMOS access transistors, 1 pair of NMOS drive transistors, and 1 pair of PMOS load transistors, a total of 3 types (6) transistors. [0004] In order to suppress the manufacturing deviation of the SRAM memory cell, and to reduce the area of ​​the memory cell and the capacitance of the bit line, a horizontal cell structure has been considered. Unlike the vertica...

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Problems solved by technology

When the potential rises too high, the data held by the low-side storage node will change to the high (side) misoperation

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