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High-speed programmable frequency-divider with synchronous reload

A frequency divider and frequency division factor technology, which is applied in the direction of pulse counters, counting chain pulse counters, electrical components, etc., can solve sensitive problems

Inactive Publication Date: 2005-02-23
NXP BV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, if figure 2 As illustrated, each edge of the MinG, MinH or MinI signal occurs in the unsafe region 290, and using any of these signals as a program load signal may result in one or more The counter stage 110 is sensitive to the programmed division factor

Method used

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  • High-speed programmable frequency-divider with synchronous reload
  • High-speed programmable frequency-divider with synchronous reload
  • High-speed programmable frequency-divider with synchronous reload

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Embodiment Construction

[0034] The invention is shown using an exemplary 8-stage programmable divider, where the stages are divided into two groups of 4 low-stage F-I and 4 high-stage J1-JLast to provide Programmable frequency division range of 32-511. As will become apparent to one of ordinary skill in the art, the principles of the present invention are not limited to a particular number of stages of frequency dividers, nor to a particular division, if any, between high and low stages in a frequency divider.

[0035] Figure 5 illustrates with Figure 1A , 1B Compared with the traditional programmable frequency divider 100 of , the programmable frequency divider 500 with selectable phase relationship between stages, and Figure 4 A timing diagram of the enable signal MinF-MinJ3 capable of dividing by 3 in the frequency divider 500 is illustrated. Each stage 120, 130 is coupled to its subsequent stage by cross-coupling the outputs Q and Q- of each stage to the clock inputs C- and C, respe...

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Abstract

A programmable-divider provides a lower-speed transition signal to effect a synchronized load of a new divisor value during a safe-load period of the programmable-divider, such that the division occurs using either the prior divisor value or the new divisor value, only. A combination of in-phase 120 and reverse-phase 230 counter stages are used to position the divisor-independent period of each counter stage so that an edge of at least one of the lower-speed counter-enabling signals occurs during a period when all of the counter stages are in a divisor-independent period. The preferred selection of in-phase and reverse-phase counter stages also maximizes the critical path duration, to allow for the accurate division of very high speed input frequencies.

Description

[0001] This application claims the benefit of US Provisional Patent Application 60 / 333,280, Attorney Docket US018192P, filed November 16, 2001. technical field [0002] The invention relates to the field of electronic equipment, in particular to a high-speed programmable frequency divider or a multi-module prescaler that can load new frequency division factors without disturbing the counting process. Background technique [0003] Figure 1A Describes a method based on "A Family of Low-Power Circuits" written by Cicero S. Vaucher et al., IEEE Journal of Solid-State Circuits, Vol.35, No.7, July 2000, incorporated herein by reference A conventional programmable frequency divider 100 or a multi-block prescaler of the principles disclosed in "Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology". The frequency divider 100 divides the frequency of the input signal In by a programmed amount. Each counter stage 110 is a programmable divide-by-2 or 3-counter. [...

Claims

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Application Information

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IPC IPC(8): H03K23/64H03K23/66
CPCH03K23/667H03K23/66
Inventor H·吴R·加斯克
Owner NXP BV
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