Data transfer memory

Abstract

A data transfer memory for reducing the number of components in an electronic module. A master controller circuit provides a transfer start command to a master clock signal generator circuit when receiving an activation detection signal from a power activation detection circuit. As a result, the master clock signal generator circuit generates a basic clock signal, outputs the basic clock signal to an SCL line, and has a master transfer sequencer circuit execute a transfer sequence. The master transfer sequencer circuit transmits a start condition, data stored in the nonvolatile memory via a serial control circuit, and a stop condition to an SDA line synchronously with the basic clock signal.

Description

technical field [0001] The present invention relates to data transfer memory. Background technique [0002] The I2C bus is a 2-wire serial bus advocated by Philips. The I2C bus corresponds to the sending command of the master device, and the slave device acts. The operation of the I2C bus will be described using Figures 6 to 10. [0003] As shown in Fig. 6, when the SCL line is "H", the SDA line changes from "H" to "L", and becomes an active state. All actions start in the start state. When the SCL line is "H", the SDA line changes from "L" to "H", and becomes a stop state. Here, the SCL line is a serial clock line for inputting a serial clock, and the SDA line is a serial data line for data transfer. [0004] The sending command is carried out by changing the SDA line during the "H" period of the SCL line, and 8 bits are sent continuously. During the ninth clock cycle, the command-accepting slave device puts the SDA line to "L" and sends an acknowledgment of acceptanc...

AI Technical Summary

Problems solved by technology

[0016] However, in the above-mentioned prior art, because the data memory can only function as a slave device, so when the data stored in the data memory is to be transmitted to

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