Method to make markers for double gate SOI processing

Abstract

Method to make at least one marker (MX) for double gate SOI processing on a SOI wafer, the at least one marker having a diffracting structure in a first direction and the diffracting structure being arranged for generating an asymmetrical diffraction pattern during use in an alignment and overlay detection system for detection in the first direction; the SOI wafer comprising a substrate, an oxidized layer on the substrate, and a semiconductor layer on top of the oxidized layer; the double gate SOI processing being performed on at least one die (D); the at least one die (D) being located on the semiconductor layer and comprising at least an inner area arranged as a circuit area (C) and an outer area arranged as scribe line area (SL); the at least one marker (MX) being defined in the scribe line area (SL); and the double gate SOI processing comprising a processing step for: separating the semiconductor layer from the oxidized layer, attaching the separated semiconductor layer as a turned-over semiconductor layer on a surface of a new substrate, with the original top surface of the semiconductor layer directed towards on the surface of the new substrate, wherein the method provides a mirrored marker (MX'), the mirrored marker (MX') being the mirror image of the marker (MX), by using a mirror operation around a second direction perpendicular to the first direction.

Description

technical field [0001] The invention relates to a method of making a mark for a dual-gate SOI process as defined in the preamble of claim 1 . Also, the present invention relates to markings for dual gate SOI processes. Further the invention relates to semiconductor devices equipped with such markings for dual gate SOI processes. Background technique [0002] Such a notation is known from US patent US 6335214 B1 which discloses an SOI (Silicon On Insulator) circuit with double gate transistors. Also disclosed is a method of fabricating a dual-gate transistor in which a backside gate of the transistor is produced which is self-aligned with a frontside gate of the transistor. [0003] A transfer method for producing a marking pattern on the backside of a wafer, the method comprising forming etch-stop spacers at the edges of the gate stack and etching alignment trenches through the silicon device layer and through the buried oxide layer such that Depositing an alignment layer...

AI Technical Summary

Problems solved by technology

[0006] However, the asymmetry of the alignment signal and its detection in the lithographic tool is a hindrance where the wafers are bonded in the dual-gate SOI process

After wafer bonding, further photolithographic processes are hampered because the signals generated by the alignment marks can no longer be detected due to the disturbed asymmetry

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