Overhang support for a stacked semiconductor device, and method of forming thereof

Abstract

A stacked, multi-die semiconductor device and method of forming thereof. A preferred embodiment comprises disposing a stack of semiconductor dies to a substrate. The stacking arrangement is such that a lateral periphery of an upper die is cantilevered over a lower die thereby forming a recess. A supporting adhesive layer containing a filler is disposed upon the substrate about the lateral periphery of the lower die and substantially filling the recess. In one preferred embodiment, the filler comprises microspheres. In another preferred embodiment, the filler comprises a dummy die, an active die, or a passive die.

Description

technical field [0001] The present invention relates to a semiconductor packaging component and its manufacturing method, in particular to a package containing stacked semiconductor chips and its manufacturing method. Background technique [0002] With the increasing demand for miniaturization, light weight and multi-functionalization of electronic components, the density of semiconductor packages is increased to reduce the size and area occupied by assembly. One of the technologies developed to meet the above requirements is to stack a plurality of bare or packaged chips in a package, such as disclosed in US Pat. No. 6,650,019. [0003] figure 1 It is a cross-sectional view showing a known semiconductor package 100 with stacked chips 102 and 104 . The package 100 is a ball grid array (ball grid array; BGA) package, and the lower surface of the substrate 110 is formed with a plurality of solder balls (solder balls; commonly referred to as "solder balls" in the industry) 10...

AI Technical Summary

Problems solved by technology

In other words, the downward stress applied by the solder pins 132 will cause the second wafer 104 to deform, resulting in separation or delamination between the lower surface of the second wafer 104 and the upper surface of the adhesive layer 128

[0014] Yet another problem that may be caused by known stacking techniques is the void area 130 between the first wafer 102 and the second wafer 104 and the deflection caused by the solder pins 132

Conductive bond wire 126 or bond pad 112 may deform itself, which may cause an open circuit between the two

In other words, during the wire bonding process, the chip 104 will be repeatedly deformed and bent, which will cause the entire package to vibrate, and the electrical connection between the conductive bonding wire 126 and the bonding pad 112 will be fatigued and damaged.

Even if there is no open circuit between the two due to fatigue damage during the process, it will still reduce the service life and reliability of the component

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