AES encrypted circuit structure for data stream executed in desequencing

Abstract

Structure of Rijindael encrypted circuit of executing in desequencing belongs to cipher IC in area of resisting analytical attack of difference power consumption. Circuit structure integrated in a chip contains the input part and the output part to accomplish expansion and expansion loop of cryptographic-key including channel switch unit, storages of initial cryptographic-key, AK temporary storage unit of arithmetic unit for expansion of cryptographic-key, and matching check unit. Circle transforming loop for converting circled cryptographic-key includes switch unit for circled updating channel, AddKey arithmetic unit, EU arithmetic unit, AK temporary storage unit and relevant check unit. Using bit-by-bit hybrid operation, row shift operation, circled iterated operation etc for circled cryptographic-key and information of state obtains cipher text, which is output through output part. The invention lowers 66% difference power consumption so as to raise difficulty of attack.

Description

Technical field: [0001] The invention is used to solve the problem of anti-differential power analysis attack of crypto integrated circuit Background technique: [0002] With the widespread application of key storage data security integrated circuits such as smart cards and pay TV cards, power analysis attacks, especially differential power attacks (DPA), have begun to appear, and have quickly become an important threat to data storage cryptographic chips. Power consumption analysis attacks are hardware-oriented attacks that process power current changes in data engineering by collecting chips and obtain data information from them. Among them, the most commonly used differential power analysis attack is to collect the working current data of multiple chips, and advance part of the key by statistically checking the power consumption sample value at each time. Making the execution time of each operation of the circuit random is one of the important ways to combat differential powe...

AI Technical Summary

Problems solved by technology

[0034] The AES algorithm is based on the Rijndael algorithm as the core. However, some features of the Rijndael algorithm have not been accepted as the AES standard. The Rijndael algorithm supports any 32-bit span packet length between 128 bits and 256 bits, but the AES standard only supports 128 bits. plaintext length, key length of 128, 192 or 256 bits

Images